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x86: Remove CONFIG_SYS_EARLY_PCI_INIT
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1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS2_RDB_H
8 #define __LS2_RDB_H
9
10 #include "ls2085a_common.h"
11
12 #undef CONFIG_CONS_INDEX
13 #define CONFIG_CONS_INDEX       2
14
15 #define CONFIG_DISPLAY_BOARDINFO
16
17 #ifndef __ASSEMBLY__
18 unsigned long get_board_sys_clk(void);
19 #endif
20
21 #define CONFIG_SYS_FSL_CLK
22 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
23 #define CONFIG_DDR_CLK_FREQ             133333333
24 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
25
26 #define CONFIG_DDR_SPD
27 #define CONFIG_DDR_ECC
28 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
29 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
30 #define SPD_EEPROM_ADDRESS1     0x51
31 #define SPD_EEPROM_ADDRESS2     0x52
32 #define SPD_EEPROM_ADDRESS3     0x53
33 #define SPD_EEPROM_ADDRESS4     0x54
34 #define SPD_EEPROM_ADDRESS5     0x55
35 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
36 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
37 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
38 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
39 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
40 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
41 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
42
43 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
44
45 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
46 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
47 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
48
49 #define CONFIG_SYS_NOR0_CSPR                                    \
50         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
51         CSPR_PORT_SIZE_16                                       | \
52         CSPR_MSEL_NOR                                           | \
53         CSPR_V)
54 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
55         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
56         CSPR_PORT_SIZE_16                                       | \
57         CSPR_MSEL_NOR                                           | \
58         CSPR_V)
59 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
60 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
61                                 FTIM0_NOR_TEADC(0x5) | \
62                                 FTIM0_NOR_TEAHC(0x5))
63 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
64                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
65                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
66 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
67                                 FTIM2_NOR_TCH(0x4) | \
68                                 FTIM2_NOR_TWPH(0x0E) | \
69                                 FTIM2_NOR_TWP(0x1c))
70 #define CONFIG_SYS_NOR_FTIM3    0x04000000
71 #define CONFIG_SYS_IFC_CCR      0x01000000
72
73 #ifndef CONFIG_SYS_NO_FLASH
74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI
76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
77 #define CONFIG_SYS_FLASH_QUIET_TEST
78 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
79
80 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
81 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
82 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
83 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
84
85 #define CONFIG_SYS_FLASH_EMPTY_INFO
86 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
87                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
88 #endif
89
90 #define CONFIG_NAND_FSL_IFC
91 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
92 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
93
94
95 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
96 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
97                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
98                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
99                                 | CSPR_V)
100 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
101
102 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
103                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
104                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
105                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
106                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
107                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
108                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
109
110 #define CONFIG_SYS_NAND_ONFI_DETECTION
111
112 /* ONFI NAND Flash mode0 Timing Params */
113 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
114                                         FTIM0_NAND_TWP(0x30)   | \
115                                         FTIM0_NAND_TWCHT(0x0e) | \
116                                         FTIM0_NAND_TWH(0x14))
117 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
118                                         FTIM1_NAND_TWBE(0xab)  | \
119                                         FTIM1_NAND_TRR(0x1c)   | \
120                                         FTIM1_NAND_TRP(0x30))
121 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
122                                         FTIM2_NAND_TREH(0x14) | \
123                                         FTIM2_NAND_TWHRE(0x3c))
124 #define CONFIG_SYS_NAND_FTIM3           0x0
125
126 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
127 #define CONFIG_SYS_MAX_NAND_DEVICE      1
128 #define CONFIG_MTD_NAND_VERIFY_WRITE
129 #define CONFIG_CMD_NAND
130
131 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
132
133 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
134 #define QIXIS_LBMAP_SWITCH              0x06
135 #define QIXIS_LBMAP_MASK                0x0f
136 #define QIXIS_LBMAP_SHIFT               0
137 #define QIXIS_LBMAP_DFLTBANK            0x00
138 #define QIXIS_LBMAP_ALTBANK             0x04
139 #define QIXIS_LBMAP_NAND                0x09
140 #define QIXIS_RST_CTL_RESET             0x31
141 #define QIXIS_RST_CTL_RESET_EN          0x30
142 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
143 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
144 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
145 #define QIXIS_RCW_SRC_NAND              0x119
146 #define QIXIS_RST_FORCE_MEM             0x01
147
148 #define CONFIG_SYS_CSPR3_EXT    (0x0)
149 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
150                                 | CSPR_PORT_SIZE_8 \
151                                 | CSPR_MSEL_GPCM \
152                                 | CSPR_V)
153 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
154                                 | CSPR_PORT_SIZE_8 \
155                                 | CSPR_MSEL_GPCM \
156                                 | CSPR_V)
157
158 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
159 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
160 /* QIXIS Timing parameters for IFC CS3 */
161 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
162                                         FTIM0_GPCM_TEADC(0x0e) | \
163                                         FTIM0_GPCM_TEAHC(0x0e))
164 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
165                                         FTIM1_GPCM_TRAD(0x3f))
166 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
167                                         FTIM2_GPCM_TCH(0xf) | \
168                                         FTIM2_GPCM_TWP(0x3E))
169 #define CONFIG_SYS_CS3_FTIM3            0x0
170
171 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
172 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
173 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
174 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
175 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
176 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
177 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
178 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
179 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
180 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
181 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
182 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
183 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
184 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
185 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
186 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
187 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
188 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
189
190 #define CONFIG_ENV_IS_IN_NAND
191 #define CONFIG_ENV_OFFSET               (2048 * 1024)
192 #define CONFIG_ENV_SECT_SIZE            0x20000
193 #define CONFIG_ENV_SIZE                 0x2000
194 #define CONFIG_SPL_PAD_TO               0x80000
195 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
196 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
197 #else
198 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
199 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
200 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
201 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
202 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
203 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
204 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
205 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
206 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
207 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
208 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
209 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
210 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
211 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
212 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
213 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
214 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
215
216 #define CONFIG_ENV_IS_IN_FLASH
217 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
218 #define CONFIG_ENV_SECT_SIZE            0x20000
219 #define CONFIG_ENV_SIZE                 0x2000
220 #endif
221
222 /* Debug Server firmware */
223 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
224 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
225
226 /* MC firmware */
227 #define CONFIG_SYS_LS_MC_FW_IN_NOR
228 #define CONFIG_SYS_LS_MC_FW_ADDR        0x580300000ULL
229
230 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
231 #define CONFIG_SYS_LS_MC_DPL_ADDR       0x580700000ULL
232
233 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
234 #define CONFIG_SYS_LS_MC_DPC_ADDR       0x580800000ULL
235
236 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
237 #define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
238 #define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR  0x580900000ULL
239
240 /*
241  * I2C
242  */
243 #define I2C_MUX_PCA_ADDR                0x75
244 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
245
246 /* I2C bus multiplexer */
247 #define I2C_MUX_CH_DEFAULT      0x8
248
249 /* SPI */
250 #ifdef CONFIG_FSL_DSPI
251 #define CONFIG_CMD_SF
252 #define CONFIG_SPI_FLASH
253 #define CONFIG_SPI_FLASH_STMICRO
254 #define CONFIG_SPI_FLASH_BAR
255 #endif
256
257 /*
258  * RTC configuration
259  */
260 #define RTC
261 #define CONFIG_RTC_DS3231               1
262 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
263 #define CONFIG_CMD_DATE
264
265 /* EEPROM */
266 #define CONFIG_ID_EEPROM
267 #define CONFIG_CMD_EEPROM
268 #define CONFIG_SYS_I2C_EEPROM_NXID
269 #define CONFIG_SYS_EEPROM_BUS_NUM       0
270 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
274
275 #define CONFIG_FSL_MEMAC
276 #define CONFIG_PCI              /* Enable PCIE */
277 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
278
279 #ifdef CONFIG_PCI
280 #define CONFIG_PCI_PNP
281 #define CONFIG_PCI_SCAN_SHOW
282 #define CONFIG_CMD_PCI
283 #endif
284
285 /*  MMC  */
286 #define CONFIG_MMC
287 #ifdef CONFIG_MMC
288 #define CONFIG_CMD_MMC
289 #define CONFIG_FSL_ESDHC
290 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
291 #define CONFIG_GENERIC_MMC
292 #define CONFIG_CMD_FAT
293 #define CONFIG_DOS_PARTITION
294 #endif
295
296 #define CONFIG_MISC_INIT_R
297
298 /*
299  * USB
300  */
301 #define CONFIG_HAS_FSL_XHCI_USB
302 #define CONFIG_USB_XHCI
303 #define CONFIG_USB_XHCI_FSL
304 #define CONFIG_USB_XHCI_DWC3
305 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
306 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
307 #define CONFIG_CMD_USB
308 #define CONFIG_USB_STORAGE
309 #define CONFIG_CMD_EXT2
310
311 /* Initial environment variables */
312 #undef CONFIG_EXTRA_ENV_SETTINGS
313 #define CONFIG_EXTRA_ENV_SETTINGS               \
314         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
315         "loadaddr=0x80100000\0"                 \
316         "kernel_addr=0x100000\0"                \
317         "ramdisk_addr=0x800000\0"               \
318         "ramdisk_size=0x2000000\0"              \
319         "fdt_high=0xa0000000\0"                 \
320         "initrd_high=0xffffffffffffffff\0"      \
321         "kernel_start=0x581100000\0"            \
322         "kernel_load=0xa0000000\0"              \
323         "kernel_size=0x2800000\0"
324
325 #undef CONFIG_BOOTARGS
326 #define CONFIG_BOOTARGS         "console=ttyS1,115200 root=/dev/ram0 " \
327                                 "earlycon=uart8250,mmio,0x21c0600,115200 " \
328                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
329                                 " hugepagesz=2m hugepages=16"
330
331 /* MAC/PHY configuration */
332 #ifdef CONFIG_FSL_MC_ENET
333 #define CONFIG_PHYLIB_10G
334 #define CONFIG_PHY_AQUANTIA
335 #define CONFIG_PHY_CORTINA
336 #define CONFIG_PHYLIB
337 #define CONFIG_SYS_CORTINA_FW_IN_NOR
338 #define CONFIG_CORTINA_FW_ADDR          0x581000000
339 #define CONFIG_CORTINA_FW_LENGTH        0x40000
340
341 #define CORTINA_PHY_ADDR1       0x10
342 #define CORTINA_PHY_ADDR2       0x11
343 #define CORTINA_PHY_ADDR3       0x12
344 #define CORTINA_PHY_ADDR4       0x13
345 #define AQ_PHY_ADDR1            0x00
346 #define AQ_PHY_ADDR2            0x01
347 #define AQ_PHY_ADDR3            0x02
348 #define AQ_PHY_ADDR4            0x03
349
350 #define CONFIG_MII
351 #define CONFIG_ETHPRIME         "DPNI1"
352 #define CONFIG_PHY_GIGE
353 #define CONFIG_PHY_AQUANTIA
354 #endif
355
356 #endif /* __LS2_RDB_H */