3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Configuation settings for the LUBBOCK board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * High Level Configuration Options
37 #define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
38 #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
41 #define CONFIG_SHARP_LM8V31
44 #define CONFIG_BOARD_LATE_INIT
45 #define CONFIG_DOS_PARTITION
46 #define CONFIG_SYS_TEXT_BASE 0x0
48 /* we will never enable dcache, because we have to setup MMU first */
49 #define CONFIG_SYS_DCACHE_OFF
52 * Size of malloc() pool
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
59 #define CONFIG_LAN91C96
60 #define CONFIG_LAN91C96_BASE 0x0C000000
63 * select serial console configuration
65 #define CONFIG_PXA_SERIAL
66 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_BAUDRATE 115200
77 #define CONFIG_BOOTP_BOOTFILESIZE
78 #define CONFIG_BOOTP_BOOTPATH
79 #define CONFIG_BOOTP_GATEWAY
80 #define CONFIG_BOOTP_HOSTNAME
84 * Command line configuration.
86 #include <config_cmd_default.h>
88 #define CONFIG_CMD_FAT
91 #define CONFIG_BOOTDELAY 3
92 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
93 #define CONFIG_NETMASK 255.255.0.0
94 #define CONFIG_IPADDR 192.168.0.21
95 #define CONFIG_SERVERIP 192.168.0.250
96 #define CONFIG_BOOTCOMMAND "bootm 80000"
97 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
98 #define CONFIG_CMDLINE_TAG
99 #define CONFIG_TIMESTAMP
101 #if defined(CONFIG_CMD_KGDB)
102 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
103 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
107 * Miscellaneous configurable options
109 #define CONFIG_SYS_HUSH_PARSER 1
111 #define CONFIG_SYS_LONGHELP /* undef to save memory */
112 #ifdef CONFIG_SYS_HUSH_PARSER
113 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
115 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
117 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
121 #define CONFIG_SYS_DEVICE_NULLDEV 1
123 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
124 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
126 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
128 #define CONFIG_SYS_HZ 1000
129 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
132 #define CONFIG_PXA_MMC
133 #define CONFIG_CMD_MMC
134 #define CONFIG_SYS_MMC_BASE 0xF0000000
138 * Physical Memory Map
140 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
141 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
142 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
143 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
144 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
145 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
146 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
147 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
148 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
150 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
151 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
152 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
153 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
154 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
156 #define CONFIG_SYS_DRAM_BASE 0xa0000000
157 #define CONFIG_SYS_DRAM_SIZE 0x04000000
159 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
161 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
162 #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
164 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
169 #define CONFIG_SYS_GPSR0_VAL 0x00008000
170 #define CONFIG_SYS_GPSR1_VAL 0x00FC0382
171 #define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
172 #define CONFIG_SYS_GPCR0_VAL 0x00000000
173 #define CONFIG_SYS_GPCR1_VAL 0x00000000
174 #define CONFIG_SYS_GPCR2_VAL 0x00000000
175 #define CONFIG_SYS_GPDR0_VAL 0x0060A800
176 #define CONFIG_SYS_GPDR1_VAL 0x00FF0382
177 #define CONFIG_SYS_GPDR2_VAL 0x0001C000
178 #define CONFIG_SYS_GAFR0_L_VAL 0x98400000
179 #define CONFIG_SYS_GAFR0_U_VAL 0x00002950
180 #define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
181 #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
182 #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
183 #define CONFIG_SYS_GAFR2_U_VAL 0x00000002
185 #define CONFIG_SYS_PSSR_VAL 0x20
187 #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
188 #define CONFIG_SYS_CKEN 0x0
193 #define CONFIG_SYS_MSC0_VAL 0x23F223F2
194 #define CONFIG_SYS_MSC1_VAL 0x3FF1A441
195 #define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
196 #define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
197 #define CONFIG_SYS_MDREFR_VAL 0x00018018
198 #define CONFIG_SYS_MDMRS_VAL 0x00000000
200 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
201 #define CONFIG_SYS_SXCNFG_VAL 0x00000000
204 * PCMCIA and CF Interfaces
206 #define CONFIG_SYS_MECR_VAL 0x00000000
207 #define CONFIG_SYS_MCMEM0_VAL 0x00010504
208 #define CONFIG_SYS_MCMEM1_VAL 0x00010504
209 #define CONFIG_SYS_MCATT0_VAL 0x00010504
210 #define CONFIG_SYS_MCATT1_VAL 0x00010504
211 #define CONFIG_SYS_MCIO0_VAL 0x00004715
212 #define CONFIG_SYS_MCIO1_VAL 0x00004715
214 #define _LED 0x08000010
215 #define LED_BLANK 0x08000040
218 * FLASH and environment organization
220 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
221 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
223 /* timeout values are in ticks */
224 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
225 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
227 /* NOTE: many default partitioning schemes assume the kernel starts at the
228 * second sector, not an environment. You have been warned!
230 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
231 #define CONFIG_ENV_IS_IN_FLASH 1
232 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
233 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
234 #define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
240 #define WHOAMI_OFFSET 0x00
241 #define HEXLED_OFFSET 0x10
242 #define BLANKLED_OFFSET 0x40
243 #define DISCRETELED_OFFSET 0x40
244 #define CNFG_SWITCHES_OFFSET 0x50
245 #define USER_SWITCHES_OFFSET 0x60
246 #define MISC_WR_OFFSET 0x80
247 #define MISC_RD_OFFSET 0x90
248 #define INT_MASK_OFFSET 0xC0
249 #define INT_CLEAR_OFFSET 0xD0
250 #define GP_OFFSET 0x100
252 #endif /* __CONFIG_H */