3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Configuation settings for the LUBBOCK board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * If we are developing, we might want to start armboot from ram
35 * so we MUST NOT initialize critical regs like mem-timing ...
37 #define CONFIG_INIT_CRITICAL /* undef for developing */
40 * High Level Configuration Options
43 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
44 #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
46 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49 * Size of malloc() pool
51 #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
58 * select serial console configuration
60 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
62 /* allow to overwrite serial and ethaddr */
63 #define CONFIG_ENV_OVERWRITE
65 #define CONFIG_BAUDRATE 115200
67 #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
69 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
70 #include <cmd_confdefs.h>
72 #define CONFIG_BOOTDELAY 3
73 #define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
74 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
75 #define CONFIG_NETMASK 255.255.0.0
76 #define CONFIG_IPADDR 192.168.0.21
77 #define CONFIG_SERVERIP 192.168.0.250
78 #define CONFIG_BOOTCOMMAND "FIXME"
80 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
81 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
82 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
86 * Miscellaneous configurable options
88 #define CFG_LONGHELP /* undef to save memory */
89 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
90 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
91 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
92 #define CFG_MAXARGS 16 /* max number of command args */
93 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
95 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
96 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
98 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
100 #define CFG_LOAD_ADDR 0xa8000000 /* default load address */
102 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
103 #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
105 /* valid baudrates */
106 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
111 * The stack sizes are set up in start.S using the settings below
113 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
114 #ifdef CONFIG_USE_IRQ
115 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
116 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
120 * Physical Memory Map
122 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
123 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
124 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
125 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
126 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
127 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
128 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
129 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
130 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
132 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
133 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
134 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
136 #define CFG_DRAM_BASE 0xa0000000
137 #define CFG_DRAM_SIZE 0x04000000
139 #define CFG_FLASH_BASE PHYS_FLASH_1
141 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
146 #define CFG_GPSR0_VAL 0x00008000
147 #define CFG_GPSR1_VAL 0x00FC0382
148 #define CFG_GPSR2_VAL 0x0001FFFF
149 #define CFG_GPCR0_VAL 0x00000000
150 #define CFG_GPCR1_VAL 0x00000000
151 #define CFG_GPCR2_VAL 0x00000000
152 #define CFG_GPDR0_VAL 0x0060A800
153 #define CFG_GPDR1_VAL 0x00FF0382
154 #define CFG_GPDR2_VAL 0x0001C000
155 #define CFG_GAFR0_L_VAL 0x98400000
156 #define CFG_GAFR0_U_VAL 0x00002950
157 #define CFG_GAFR1_L_VAL 0x000A9558
158 #define CFG_GAFR1_U_VAL 0x0005AAAA
159 #define CFG_GAFR2_L_VAL 0xA0000000
160 #define CFG_GAFR2_U_VAL 0x00000002
162 #define CFG_PSSR_VAL 0x20
167 #define CFG_MSC0_VAL 0x23F223F2
168 #define CFG_MSC1_VAL 0x3FF1A441
169 #define CFG_MSC2_VAL 0x7FF17FF1
170 #define CFG_MDCNFG_VAL 0x00001AC9
171 #define CFG_MDREFR_VAL 0x000BC018
172 #define CFG_MDREFR_VAL_100 0x00018018
173 #define CFG_MDMRS_VAL 0x00000000
176 * PCMCIA and CF Interfaces
178 #define CFG_MECR_VAL 0x00000000
179 #define CFG_MCMEM0_VAL 0x00010504
180 #define CFG_MCMEM1_VAL 0x00010504
181 #define CFG_MCATT0_VAL 0x00010504
182 #define CFG_MCATT1_VAL 0x00010504
183 #define CFG_MCIO0_VAL 0x00004715
184 #define CFG_MCIO1_VAL 0x00004715
186 #define _LED 0x08000010
187 #define LED_BLANK (0x08000040)
190 * FLASH and environment organization
192 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
193 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
195 /* timeout values are in ticks */
196 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
197 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
200 #define CFG_ENV_IS_IN_FLASH 1
201 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
202 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
208 #define WHOAMI_OFFSET 0x00
209 #define HEXLED_OFFSET 0x10
210 #define BLANKLED_OFFSET 0x40
211 #define DISCRETELED_OFFSET 0x40
212 #define CNFG_SWITCHES_OFFSET 0x50
213 #define USER_SWITCHES_OFFSET 0x60
214 #define MISC_WR_OFFSET 0x80
215 #define MISC_RD_OFFSET 0x90
216 #define INT_MASK_OFFSET 0xC0
217 #define INT_CLEAR_OFFSET 0xD0
218 #define GP_OFFSET 0x100
220 #endif /* __CONFIG_H */