2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
4 * Based on omap3_evm_config.h
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_OMAP /* in a TI OMAP core */
16 #define CONFIG_OMAP3_MCX /* working with mcx */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
24 #define MACH_TYPE_MCX 3656
25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX
26 #define CONFIG_BOARD_LATE_INIT
28 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
30 #include <asm/arch/cpu.h> /* get chip and board defs */
31 #include <asm/arch/omap.h>
34 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
35 * and older u-boot.bin with the new U-Boot SPL.
37 #define CONFIG_SYS_TEXT_BASE 0x80008000
40 #define V_OSCK 26000000 /* Clock output from T2 */
41 #define V_SCLK (V_OSCK >> 1)
43 #define CONFIG_MISC_INIT_R
45 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
46 #define CONFIG_SETUP_MEMORY_TAGS
47 #define CONFIG_INITRD_TAG
48 #define CONFIG_REVISION_TAG
51 * Size of malloc() pool
53 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
54 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
65 * NS16550 Configuration
67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
71 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
74 * select serial console configuration
76 #define CONFIG_CONS_INDEX 3
77 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
78 #define CONFIG_SERIAL3 3 /* UART3 */
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
86 #define CONFIG_OMAP_HSMMC
87 #define CONFIG_GENERIC_MMC
88 #define CONFIG_DOS_PARTITION
91 #define CONFIG_OMAP3_GPIO_2
92 #define CONFIG_OMAP3_GPIO_5
93 #define CONFIG_USB_EHCI
94 #define CONFIG_USB_EHCI_OMAP
95 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
96 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
97 #define CONFIG_USB_HOST_ETHER
98 #define CONFIG_USB_ETHER_ASIX
99 #define CONFIG_USB_ETHER_MCS7830
101 /* commands to include */
102 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
104 #define CONFIG_CMD_DATE
105 #define CONFIG_CMD_NAND /* NAND support */
106 #define CONFIG_CMD_UBIFS
107 #define CONFIG_RBTREE
109 #define CONFIG_MTD_PARTITIONS
110 #define CONFIG_MTD_DEVICE
111 #define CONFIG_CMD_MTDPARTS
113 #define CONFIG_SYS_NO_FLASH
114 #define CONFIG_SYS_I2C
115 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
116 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
117 #define CONFIG_SYS_I2C_OMAP34XX
120 #define CONFIG_RTC_DS1337
121 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
126 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
128 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
132 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
134 #define CONFIG_JFFS2_NAND
135 /* nand device jffs2 lives on */
136 #define CONFIG_JFFS2_DEV "nand0"
137 /* start of jffs2 partition */
138 #define CONFIG_JFFS2_PART_OFFSET 0x680000
139 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
141 /* Environment information */
143 #define CONFIG_BOOTFILE "uImage"
145 /* Setup MTD for NAND on the SOM */
146 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
147 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
148 "1m(u-boot),256k(env1)," \
149 "256k(env2),6m(kernel),6m(k_recovery)," \
150 "8m(fs_recovery),-(common_data)"
152 #define CONFIG_HOSTNAME mcx
153 #define CONFIG_EXTRA_ENV_SETTINGS \
154 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
155 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
156 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
157 "addfb=setenv bootargs ${bootargs} vram=6M " \
158 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
159 "addip_sta=setenv bootargs ${bootargs} " \
160 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
161 "${netmask}:${hostname}:eth0:off\0" \
162 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
163 "addip=if test -n ${ipdyn};then run addip_dyn;" \
164 "else run addip_sta;fi\0" \
165 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
166 "addtty=setenv bootargs ${bootargs} " \
167 "console=${consoledev},${baudrate}\0" \
168 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
169 "baudrate=115200\0" \
170 "consoledev=ttyO2\0" \
171 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
172 "loadaddr=0x82000000\0" \
173 "load=tftp ${loadaddr} ${u-boot}\0" \
174 "load_k=tftp ${loadaddr} ${bootfile}\0" \
175 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
176 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
177 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
178 "mmcargs=root=/dev/mmcblk0p2 rw " \
179 "rootfstype=ext3 rootwait\0" \
180 "mmcboot=echo Booting from mmc ...; " \
182 "run addip addtty addmtd addfb addeth addmisc;" \
184 "bootm ${loadaddr}\0" \
185 "net_nfs=run load_k; " \
187 "run addip addtty addmtd addfb addeth addmisc;" \
188 "bootm ${loadaddr}\0" \
189 "nfsargs=setenv bootargs root=/dev/nfs rw " \
190 "nfsroot=${serverip}:${rootpath}\0" \
191 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
192 "uboot_addr=0x80000\0" \
193 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
194 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
195 "updatemlo=nandecc hw;nand erase 0 20000;" \
196 "nand write ${loadaddr} 0 20000\0" \
197 "upd=if run load;then echo Updating u-boot;if run update;" \
198 "then echo U-Boot updated;" \
199 "else echo Error updating u-boot !;" \
200 "echo Board without bootloader !!;" \
202 "else echo U-Boot not downloaded..exiting;fi\0" \
203 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
204 "bootscript=echo Running bootscript from mmc ...; " \
205 "source ${loadaddr}\0" \
206 "nandargs=setenv bootargs ubi.mtd=7 " \
207 "root=ubi0:rootfs rootfstype=ubifs\0" \
208 "nandboot=echo Booting from nand ...; " \
210 "ubi part nand0,4;" \
211 "ubi readvol ${loadaddr} kernel;" \
212 "run addtty addmtd addfb addeth addmisc;" \
213 "bootm ${loadaddr}\0" \
214 "preboot=ubi part nand0,7;" \
215 "ubi readvol ${loadaddr} splash;" \
216 "bmp display ${loadaddr};" \
218 "swupdate_args=setenv bootargs root=/dev/ram " \
219 "quiet loglevel=1 " \
220 "consoleblank=0 ${swupdate_misc}\0" \
221 "swupdate=echo Running Sw-Update...;" \
222 "if printenv mtdparts;then echo Starting SwUpdate...; " \
223 "else mtdparts default;fi; " \
224 "ubi part nand0,5;" \
225 "ubi readvol 0x82000000 kernel_recovery;" \
226 "ubi part nand0,6;" \
227 "ubi readvol 0x84000000 fs_recovery;" \
228 "run swupdate_args; " \
229 "setenv bootargs ${bootargs} " \
231 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
232 "omapdss.def_disp=lcd;" \
233 "bootm 0x82000000 0x84000000\0" \
234 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
235 "then source 82000000;else run nandboot;fi\0"
237 #define CONFIG_AUTO_COMPLETE
238 #define CONFIG_CMDLINE_EDITING
241 * Miscellaneous configurable options
243 #define CONFIG_SYS_LONGHELP /* undef to save memory */
244 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
245 /* Print Buffer Size */
246 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
247 sizeof(CONFIG_SYS_PROMPT) + 16)
248 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
250 /* Boot Argument Buffer Size */
251 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
252 /* memtest works on */
253 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
254 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
255 0x01F00000) /* 31MB */
257 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
259 #define CONFIG_PREBOOT
262 * AM3517 has 12 GP timers, they can be driven by the system clock
263 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
264 * This rate is divided by a local divisor.
266 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
267 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
270 * Physical Memory Map
272 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
273 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
274 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
277 * FLASH and environment organization
280 /* **** PISMO SUPPORT *** */
282 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
283 #define CONFIG_NAND_OMAP_GPMC
284 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
285 #define CONFIG_ENV_IS_IN_NAND
286 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
288 /* Redundant Environment */
289 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
290 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
291 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
292 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
293 2 * CONFIG_SYS_ENV_SECT_SIZE)
294 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
296 /* Flash banks JFFS2 should use */
297 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
298 CONFIG_SYS_MAX_NAND_DEVICE)
299 #define CONFIG_SYS_JFFS2_MEM_NAND
300 /* use flash_info[2] */
301 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
302 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
304 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
305 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
306 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
307 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
308 CONFIG_SYS_INIT_RAM_SIZE - \
309 GENERATED_GBL_DATA_SIZE)
311 /* Defines for SPL */
312 #define CONFIG_SPL_FRAMEWORK
313 #define CONFIG_SPL_BOARD_INIT
314 #define CONFIG_SPL_NAND_SIMPLE
316 #define CONFIG_SPL_NAND_BASE
317 #define CONFIG_SPL_NAND_DRIVERS
318 #define CONFIG_SPL_NAND_ECC
319 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
321 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
322 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
323 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
325 /* move malloc and bss high to prevent clashing with the main image */
326 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
327 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
328 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
329 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
331 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
332 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
334 /* NAND boot config */
335 #define CONFIG_SYS_NAND_PAGE_COUNT 64
336 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
337 #define CONFIG_SYS_NAND_OOBSIZE 64
338 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
339 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
340 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
341 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
342 48, 49, 50, 51, 52, 53, 54, 55,\
343 56, 57, 58, 59, 60, 61, 62, 63}
344 #define CONFIG_SYS_NAND_ECCSIZE 256
345 #define CONFIG_SYS_NAND_ECCBYTES 3
346 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
347 #define CONFIG_SPL_NAND_SOFTECC
349 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
351 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
357 #if defined(CONFIG_CMD_NET)
358 #define CONFIG_DRIVER_TI_EMAC
359 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
361 #define CONFIG_BOOTP_DNS
362 #define CONFIG_BOOTP_DNS2
363 #define CONFIG_BOOTP_SEND_HOSTNAME
364 #define CONFIG_NET_RETRY_COUNT 10
367 #define CONFIG_SPLASH_SCREEN
368 #define CONFIG_VIDEO_BMP_RLE8
369 #define CONFIG_CMD_BMP
370 #define CONFIG_VIDEO_OMAP3
372 #endif /* __CONFIG_H */