3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
39 /* include common defines/options for all Keymile boards */
40 #include "keymile-common.h"
42 #define CONFIG_8xx_GCLK_FREQ 66000000
44 #define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
45 #define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
46 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the
49 * default value is not working */
51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
55 #define CONFIG_EXTRA_ENV_SETTINGS \
57 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
59 "nfsroot=${serverip}:${rootpath}\0" \
60 "ramargs=setenv bootargs root=/dev/ram rw\0" \
61 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off panic=1\0" \
64 "flash_nfs=run nfsargs addip;" \
65 "bootm ${kernel_addr}\0" \
66 "flash_self=run ramargs addip;" \
67 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
68 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
69 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
70 "bootm ${kernel_addr} - ${fdt_addr}\0" \
71 "rootpath=/opt/eldk/ppc_8xx\0" \
72 "bootfile=/tftpboot/mgsuvd/uImage\0" \
74 "kernel_addr=200000\0" \
75 "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
76 "load=tftp 200000 ${u-boot}\0" \
77 "update=protect off f0000000 +${filesize};" \
78 "erase f0000000 +${filesize};" \
79 "cp.b 200000 f0000000 ${filesize};" \
80 "protect on f0000000 +${filesize}\0" \
83 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
85 #define CONFIG_TIMESTAMP /* but print image timestmps */
88 * Low Level Configuration Settings
89 * (address mappings, register initial values, etc.)
90 * You should know what you are doing if you make changes here.
92 /*-----------------------------------------------------------------------
93 * Internal Memory Mapped Register
95 #define CONFIG_SYS_IMMR 0xFFF00000
97 /*-----------------------------------------------------------------------
98 * Definitions for initial stack pointer and data area (in DPRAM)
100 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
101 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
102 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
103 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106 /*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
111 #define CONFIG_SYS_SDRAM_BASE 0x00000000
112 #define CONFIG_SYS_FLASH_BASE 0xf0000000
113 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
115 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
118 * For booting Linux, the board info and command line data
119 * have to be in the first 8 MB of memory, since this is
120 * the maximum mapped by the Linux kernel during initialization.
122 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
124 /*-----------------------------------------------------------------------
127 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
128 #define CONFIG_SYS_FLASH_SIZE 32
129 #define CONFIG_SYS_FLASH_CFI
130 #define CONFIG_FLASH_CFI_DRIVER
131 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
134 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
137 #define CONFIG_ENV_IS_IN_FLASH 1
138 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
139 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
140 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
142 /* Address and size of Redundant Environment Sector */
143 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
144 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
146 /*-----------------------------------------------------------------------
147 * Cache Configuration
149 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
150 #if defined(CONFIG_CMD_KGDB)
151 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
154 /*-----------------------------------------------------------------------
155 * SYPCR - System Protection Control 11-9
156 * SYPCR can only be written once after reset!
157 *-----------------------------------------------------------------------
158 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
160 #define CONFIG_SYS_SYPCR 0xffffff89
162 /*-----------------------------------------------------------------------
163 * SIUMCR - SIU Module Configuration 11-6
164 *-----------------------------------------------------------------------
166 #define CONFIG_SYS_SIUMCR 0x00610480
168 /*-----------------------------------------------------------------------
169 * TBSCR - Time Base Status and Control 11-26
170 *-----------------------------------------------------------------------
171 * Clear Reference Interrupt Status, Timebase freezing enabled
173 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
175 /*-----------------------------------------------------------------------
176 * PISCR - Periodic Interrupt Status and Control 11-31
177 *-----------------------------------------------------------------------
178 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
180 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
182 /*-----------------------------------------------------------------------
183 * SCCR - System Clock and reset Control Register 15-27
184 *-----------------------------------------------------------------------
185 * Set clock output, timebase and RTC source and divider,
186 * power management and some other internal clocks
188 #define SCCR_MASK 0x01800000
189 #define CONFIG_SYS_SCCR 0x01800000
191 #define CONFIG_SYS_DER 0
194 * Init Memory Controller:
196 * BR0/1 and OR0/1 (FLASH)
199 #define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
201 /* used to re-map FLASH both when starting from SRAM or FLASH:
202 * restrict access enough to keep SRAM working (if any)
203 * but not too much to meddle with FLASH accesses
205 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
206 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
209 * FLASH timing: Default value of OR0 after reset
211 #define CONFIG_SYS_OR0_PRELIM 0xfe000954
212 #define CONFIG_SYS_BR0_PRELIM 0xf0000401
215 * BR1 and OR1 (SDRAM)
218 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
219 #define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
221 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
222 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
224 #define CONFIG_SYS_OR1_PRELIM 0xfc000800
225 #define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
227 #define CONFIG_SYS_MPTPR 0x0200
228 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
229 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
230 #define CONFIG_SYS_MBMR 0x10964111
231 #define CONFIG_SYS_MAR 0x00000088
234 * 4096 Rows from SDRAM example configuration
235 * 1000 factor s -> ms
236 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
237 * 4 Number of refresh cycles per period
238 * 64 Refresh cycle in ms per number of rows
240 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
242 /* GPIO/PIGGY on CS3 initialization values
244 #define CONFIG_SYS_PIGGY_BASE (0x30000000)
245 #define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
246 #define CONFIG_SYS_BR3_PRELIM (0x30000401)
249 * Internal Definitions
253 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
254 #define BOOTFLAG_WARM 0x02 /* Software reboot */
256 #define CONFIG_SCC3_ENET
257 #define CONFIG_ETHPRIME "SCC ETHERNET"
258 #define CONFIG_HAS_ETH0
260 /* pass open firmware flat tree */
261 #define CONFIG_OF_LIBFDT 1
262 #define CONFIG_OF_BOARD_SETUP 1
264 #define OF_STDOUT_PATH "/soc/cpm/serial@a80"
266 /* enable I2C and select the hardware/software driver */
267 #undef CONFIG_HARD_I2C /* I2C with hardware support */
268 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
269 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
270 #define CONFIG_SYS_I2C_SLAVE 0x7F
271 #define I2C_SOFT_DECLARATIONS
274 * Software (bit-bang) I2C driver configuration
276 #define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
277 #define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
281 #define SDA_CONF 0x1000
282 #define SCL_CONF 0x2000
284 #define I2C_ACTIVE do {} while (0)
285 #define I2C_TRISTATE do {} while (0)
286 #define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
287 #define I2C_SDA(bit) if(bit) { \
288 clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
290 clrbits(8, I2C_BASE_PORT, SDA_BIT); \
291 setbits(be16, I2C_BASE_DIR, SDA_CONF); \
293 #define I2C_SCL(bit) if(bit) { \
294 clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
296 clrbits(8, I2C_BASE_PORT, SCL_BIT); \
297 setbits(be16, I2C_BASE_DIR, SCL_CONF); \
299 #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
301 #define CONFIG_I2C_MULTI_BUS 1
302 #define CONFIG_I2C_CMD_TREE 1
303 #define CONFIG_SYS_MAX_I2C_BUS 2
304 #define CONFIG_SYS_I2C_INIT_BOARD 1
305 #define CONFIG_I2C_MUX 1
308 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
309 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
310 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
311 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
312 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
314 /* Support the IVM EEprom */
315 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50
316 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
317 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
319 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
320 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
321 #define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
322 #define CONFIG_SYS_DTT_MAX_TEMP 70
323 #define CONFIG_SYS_DTT_LOW_TEMP -30
324 #define CONFIG_SYS_DTT_HYSTERESIS 3
325 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
327 #endif /* __CONFIG_H */