2 * (C) Copyright 2007-2010 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/xilinx/microblaze-generic/xparameters.h"
15 #define MICROBLAZE_V5 1
17 /* linear and spi flash memory */
18 #ifdef XILINX_FLASH_START
21 #undef RAMENV /* hold environment in flash */
23 #ifdef XILINX_SPI_FLASH_BASEADDR
26 #undef RAMENV /* hold environment in flash */
30 #define RAMENV /* hold environment in RAM */
35 # define CONFIG_BAUDRATE 115200
36 /* The following table includes the supported baudrates */
37 # define CONFIG_SYS_BAUDRATE_TABLE \
38 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
40 /* setting reset address */
41 /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
44 #ifdef XILINX_GPIO_BASEADDR
45 # define CONFIG_XILINX_GPIO
46 # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
49 /* interrupt controller */
50 #ifdef XILINX_INTC_BASEADDR
51 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
52 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
56 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
57 # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
58 # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
62 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
63 # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
64 # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
65 # ifndef CONFIG_SPL_BUILD
66 # define CONFIG_HW_WATCHDOG
67 # define CONFIG_XILINX_TB_WATCHDOG
71 #if !defined(CONFIG_OF_CONTROL) || \
72 (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
73 /* ddr sdram - main memory */
74 # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
75 # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
78 #define CONFIG_SYS_MALLOC_LEN 0xC0000
80 /* Stack location before relocation */
81 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
82 CONFIG_SYS_MALLOC_F_LEN)
85 * CFI flash memory layout - Example
86 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
87 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
89 * SECT_SIZE = 0x20000; 128kB is one sector
90 * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
92 * 0x2200_0000 CONFIG_SYS_FLASH_BASE
94 * 0x2204_0000 CONFIG_ENV_ADDR
98 * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
103 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
104 # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
105 # define CONFIG_SYS_FLASH_CFI 1
106 # define CONFIG_FLASH_CFI_DRIVER 1
108 # define CONFIG_SYS_FLASH_EMPTY_INFO 1
109 /* max number of memory banks */
110 # define CONFIG_SYS_MAX_FLASH_BANKS 1
111 /* max number of sectors on one chip */
112 # define CONFIG_SYS_MAX_FLASH_SECT 512
113 /* hardware flash protection */
114 # define CONFIG_SYS_FLASH_PROTECTION
115 /* use buffered writes (20x faster) */
116 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
118 # define CONFIG_ENV_IS_NOWHERE 1
119 # define CONFIG_ENV_SIZE 0x1000
120 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
122 # else /* FLASH && !RAMENV */
123 # define CONFIG_ENV_IS_IN_FLASH 1
124 /* 128K(one sector) for env */
125 # define CONFIG_ENV_SECT_SIZE 0x20000
126 # define CONFIG_ENV_ADDR \
127 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
128 # define CONFIG_ENV_SIZE 0x20000
129 # endif /* FLASH && !RAMBOOT */
133 # define CONFIG_SYS_NO_FLASH 1
134 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
135 # define CONFIG_SPI 1
136 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
137 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
138 # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
141 # define CONFIG_ENV_IS_NOWHERE 1
142 # define CONFIG_ENV_SIZE 0x1000
143 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
145 # else /* SPIFLASH && !RAMENV */
146 # define CONFIG_ENV_IS_IN_SPI_FLASH 1
147 # define CONFIG_ENV_SPI_MODE SPI_MODE_3
148 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
149 # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
150 /* 128K(two sectors) for env */
151 # define CONFIG_ENV_SECT_SIZE 0x10000
152 # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
153 /* Warning: adjust the offset in respect of other flash content and size */
154 # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
155 # endif /* SPIFLASH && !RAMBOOT */
156 #else /* !SPIFLASH */
159 # define CONFIG_SYS_NO_FLASH 1
160 # define CONFIG_ENV_IS_NOWHERE 1
161 # define CONFIG_ENV_SIZE 0x1000
162 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
163 #endif /* !SPIFLASH */
166 #if defined(XILINX_USE_ICACHE)
167 # define CONFIG_ICACHE
169 # undef CONFIG_ICACHE
172 #if defined(XILINX_USE_DCACHE)
173 # define CONFIG_DCACHE
175 # undef CONFIG_DCACHE
178 #ifndef XILINX_DCACHE_BYTE_SIZE
179 #define XILINX_DCACHE_BYTE_SIZE 32768
185 #define CONFIG_BOOTP_BOOTFILESIZE
186 #define CONFIG_BOOTP_BOOTPATH
187 #define CONFIG_BOOTP_GATEWAY
188 #define CONFIG_BOOTP_HOSTNAME
191 * Command line configuration.
193 #define CONFIG_CMD_ASKENV
194 #define CONFIG_CMD_IRQ
195 #define CONFIG_CMD_MFSL
197 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
198 # define CONFIG_CMD_CACHE
200 # undef CONFIG_CMD_CACHE
204 # define CONFIG_CMD_JFFS2
205 # define CONFIG_CMD_UBI
206 # undef CONFIG_CMD_UBIFS
208 # if !defined(RAMENV)
209 # define CONFIG_CMD_SAVES
213 #if defined(SPIFLASH)
214 # define CONFIG_CMD_SF
216 # if !defined(RAMENV)
217 # define CONFIG_CMD_SAVES
220 # undef CONFIG_CMD_JFFS2
221 # undef CONFIG_CMD_UBI
222 # undef CONFIG_CMD_UBIFS
226 #if defined(CONFIG_CMD_JFFS2)
227 # define CONFIG_MTD_PARTITIONS
230 #if defined(CONFIG_CMD_UBIFS)
231 # define CONFIG_CMD_UBI
235 #if defined(CONFIG_CMD_UBI)
236 # define CONFIG_MTD_PARTITIONS
237 # define CONFIG_RBTREE
240 #if defined(CONFIG_MTD_PARTITIONS)
242 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
243 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
244 #define CONFIG_FLASH_CFI_MTD
245 #define MTDIDS_DEFAULT "nor0=flash-0"
247 /* default mtd partition table */
248 #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
249 "256k(env),3m(kernel),1m(romfs),"\
250 "1m(cramfs),-(jffs2)"
253 /* size of console buffer */
254 #define CONFIG_SYS_CBSIZE 512
255 /* print buffer size */
256 #define CONFIG_SYS_PBSIZE \
257 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
258 /* max number of command args */
259 #define CONFIG_SYS_MAXARGS 15
260 #define CONFIG_SYS_LONGHELP
261 /* default load address */
262 #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
264 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
265 #define CONFIG_BOOTARGS "root=romfs"
266 #define CONFIG_HOSTNAME XILINX_BOARD_NAME
267 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
268 #define CONFIG_IPADDR 192.168.0.3
269 #define CONFIG_SERVERIP 192.168.0.5
270 #define CONFIG_GATEWAYIP 192.168.0.1
272 /* architecture dependent code */
273 #define CONFIG_SYS_USR_EXCEP /* user exception */
275 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
277 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
279 "mtdparts=mtdparts=flash-0:"\
280 "256k(u-boot),256k(env),3m(kernel),"\
281 "1m(romfs),1m(cramfs),-(jffs2)\0"\
282 "nc=setenv stdout nc;"\
283 "setenv stdin nc\0" \
284 "serial=setenv stdout serial;"\
285 "setenv stdin serial\0"
287 #define CONFIG_CMDLINE_EDITING
289 #define CONFIG_NETCONSOLE
290 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
292 /* Use the HUSH parser */
293 #define CONFIG_SYS_HUSH_PARSER
295 /* Enable flat device tree support */
297 #define CONFIG_OF_LIBFDT 1
299 #if defined(CONFIG_XILINX_AXIEMAC)
300 # define CONFIG_MII 1
301 # define CONFIG_CMD_MII 1
302 # define CONFIG_PHY_GIGE 1
303 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
304 # define CONFIG_PHY_ATHEROS 1
305 # define CONFIG_PHY_BROADCOM 1
306 # define CONFIG_PHY_DAVICOM 1
307 # define CONFIG_PHY_LXT 1
308 # define CONFIG_PHY_MARVELL 1
309 # define CONFIG_PHY_MICREL 1
310 # define CONFIG_PHY_MICREL_KSZ9021
311 # define CONFIG_PHY_NATSEMI 1
312 # define CONFIG_PHY_REALTEK 1
313 # define CONFIG_PHY_VITESSE 1
316 # undef CONFIG_CMD_MII
320 #define CONFIG_CMD_SPL
321 #define CONFIG_SPL_FRAMEWORK
322 #define CONFIG_SPL_LIBCOMMON_SUPPORT
323 #define CONFIG_SPL_LIBGENERIC_SUPPORT
324 #define CONFIG_SPL_SERIAL_SUPPORT
325 #define CONFIG_SPL_BOARD_INIT
327 #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
329 #define CONFIG_SPL_RAM_DEVICE
330 #ifdef CONFIG_SYS_FLASH_BASE
331 # define CONFIG_SPL_NOR_SUPPORT
332 # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
335 /* for booting directly linux */
336 #define CONFIG_SPL_OS_BOOT
338 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
340 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
342 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
345 /* SP location before relocation, must use scratch RAM */
347 #define CONFIG_SYS_INIT_RAM_ADDR 0x0
348 /* BRAM size - will be generated */
349 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000
351 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
352 CONFIG_SYS_INIT_RAM_SIZE - \
353 CONFIG_SYS_MALLOC_F_LEN)
355 /* Just for sure that there is a space for stack */
356 #define CONFIG_SPL_STACK_SIZE 0x100
358 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
360 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
361 CONFIG_SYS_INIT_RAM_ADDR - \
362 CONFIG_SYS_MALLOC_F_LEN - \
363 CONFIG_SPL_STACK_SIZE)
365 #endif /* __CONFIG_H */