3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
8 * (C) Copyright 2009-2010
9 * Michel Pollet <buserror@gmail.com>
12 * Gabriel Huau <contact@huau-gabriel.fr>
14 * Configuation settings for the MINI2440 board.
16 * SPDX-License-Identifier: GPL-2.0+
22 #define CONFIG_SYS_TEXT_BASE 0x0
23 #define CONFIG_S3C2440_GPIO
26 * High Level Configuration Options
28 #define CONFIG_ARM920T /* This is an ARM920T Core */
29 #define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
30 #define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
31 #define CONFIG_MINI2440 /* on a MIN2440 Board */
33 #define MACH_TYPE_MINI2440 1999
34 #define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
37 * We don't use lowlevel_init
39 #define CONFIG_SKIP_LOWLEVEL_INIT
40 #define CONFIG_BOARD_EARLY_INIT_F
45 /* MINI2440 has 12.0000MHz input clock */
46 #define CONFIG_SYS_CLK_FREQ 12000000
49 * Size of malloc() pool
51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
56 #define CONFIG_DRIVER_DM9000
57 #define CONFIG_DRIVER_DM9000_NO_EEPROM
58 #define CONFIG_DM9000_BASE 0x20000300
59 #define DM9000_IO CONFIG_DM9000_BASE
60 #define DM9000_DATA (CONFIG_DM9000_BASE+4)
63 * select serial console configuration
65 #define CONFIG_S3C24X0_SERIAL
66 #define CONFIG_SERIAL1
69 * allow to overwrite serial and ethaddr
71 #define CONFIG_ENV_OVERWRITE
76 #include <config_cmd_default.h>
78 #define CONFIG_CMD_DHCP
79 #define CONFIG_CMD_PORTIO
80 #define CONFIG_CMD_REGINFO
81 #define CONFIG_CMD_SAVES
84 * Miscellaneous configurable options
86 #define CONFIG_LONGHELP
87 #define CONFIG_SYS_PROMPT "MINI2440 => "
88 #define CONFIG_SYS_CBSIZE 256
89 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
90 #define CONFIG_SYS_MAXARGS 32
91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
93 #define CONFIG_SYS_MEMTEST_START 0x30000000
94 #define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
96 /* default load address */
97 #define CONFIG_SYS_LOAD_ADDR 0x32000000
99 /* boot parameters address */
100 #define CONFIG_BOOT_PARAM_ADDR 0x30000100
103 * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
104 * it to wrap 100 times (total 1562500) to get 1 sec.
106 #define CONFIG_SYS_HZ 1562500
111 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
112 #define CONFIG_BAUDRATE 115200
116 * The stack sizes are set up in start.S using the settings below
118 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
119 #ifdef CONFIG_USE_IRQ
120 #define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
121 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
125 * Physical Memory Map
127 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
128 #define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
129 #define CONFIG_SYS_SDRAM_BASE 0x30000000
130 #define CONFIG_SYS_FLASH_BASE 0x0
133 * Stack should be on the SRAM because
136 #define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
139 * NOR FLASH organization
140 * Now uses the standard CFI interface
141 * FLASH and environment organization
143 #define CONFIG_SYS_FLASH_CFI
144 #define CONFIG_FLASH_CFI_DRIVER
145 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
146 #define CONFIG_SYS_MONITOR_BASE 0x0
147 /* max number of memory banks */
148 #define CONFIG_SYS_MAX_FLASH_BANKS 1
149 /* 512 * 4096 sectors, or 32 * 64k blocks */
150 #define CONFIG_SYS_MAX_FLASH_SECT 512
151 #define CONFIG_FLASH_SHOW_PROGRESS 1
154 * Config for NOR flash
156 #define CONFIG_ENV_IS_IN_FLASH
157 #define CONFIG_MY_ENV_OFFSET 0x40000
158 /* addr of environment */
159 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
160 /* 16k Total Size of Environment Sector */
161 #define CONFIG_ENV_SIZE 0x4000
163 /* ATAG configuration */
164 #define CONFIG_INITRD_TAG
165 #define CONFIG_SETUP_MEMORY_TAGS
166 #define CONFIG_CMDLINE_TAG
167 #define CONFIG_CMDLINE_EDITING
168 #define CONFIG_AUTO_COMPLETE
170 #endif /* __CONFIG_H */