2 * Copyright (c) 2005 Freescale Semiconductor, Inc.
5 * Alex Bounine , Tundra Semiconductor Corp.
6 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board specific configuration options for Freescale
29 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
38 /* Board Configuration Definitions */
39 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
41 #define CONFIG_MPC7448HPC2
44 #define CONFIG_750FX /* this option to enable init of extended BATs */
45 #define CONFIG_ALTIVEC /* undef to disable */
47 #define CFG_BOARD_NAME "MPC7448 HPC II"
48 #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
50 #define CFG_OCN_CLK 133000000 /* 133 MHz */
51 #define CFG_CONFIG_BUS_CLK 133000000
53 #define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
55 #undef CONFIG_ECC /* disable ECC support */
57 /* Board-specific Initialization Functions to be called */
58 #define CFG_BOARD_ASM_INIT
59 #define CONFIG_BOARD_EARLY_INIT_F
60 #define CONFIG_BOARD_EARLY_INIT_R
61 #define CONFIG_MISC_INIT_R
63 #define CONFIG_HAS_ETH1
65 #define CONFIG_ENV_OVERWRITE
68 * High Level Configuration Options
72 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
74 /*#define CFG_HUSH_PARSER */
75 #undef CFG_HUSH_PARSER
77 #define CFG_PROMPT_HUSH_PS2 "> "
79 /* Pass open firmware flat tree */
80 #define CONFIG_OF_FLAT_TREE 1
81 #define CONFIG_OF_BOARD_SETUP 1
83 /* maximum size of the flat tree (8K) */
84 #define OF_FLAT_TREE_MAX_SIZE 8192
86 #define OF_CPU "PowerPC,7448@0"
87 #define OF_TSI "tsi108@c0000000"
88 #define OF_TBCLK (bd->bi_busfreq / 8)
89 #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
92 * The following defines let you select what serial you want to use
93 * for your console driver.
96 * If you have hacked a serial cable onto the second DUART channel,
97 * change the CFG_DUART port from 1 to 0 below.
101 #define CONFIG_CONS_INDEX 1
103 #define CFG_NS16550_SERIAL
104 #define CFG_NS16550_REG_SIZE 1
105 #define CFG_NS16550_CLK CFG_OCN_CLK * 8
107 #define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808)
108 #define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08)
109 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
111 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
112 #define CONFIG_ZERO_BOOTDELAY_CHECK
114 #undef CONFIG_BOOTARGS
115 /* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
116 * to mount root filesystem over NFS;echo" */
118 #if (CONFIG_BOOTDELAY >= 0)
119 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
120 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
121 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
123 #define CONFIG_BOOTARGS "console=ttyS0,115200"
126 #undef CONFIG_EXTRA_ENV_SETTINGS
128 #define CONFIG_SERIAL "No. 1"
130 /* Networking Configuration */
132 #define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
134 #define CONFIG_TSI108_ETH
135 #define CONFIG_TSI108_ETH_NUM_PORTS 2
137 #define CONFIG_NET_MULTI
139 #define CONFIG_BOOTFILE zImage.initrd.elf
140 #define CONFIG_LOADADDR 0x400000
142 /*-------------------------------------------------------------------------- */
144 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
145 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
147 #undef CONFIG_WATCHDOG /* watchdog disabled */
149 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
150 CONFIG_BOOTP_BOOTFILESIZE)
152 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
166 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
167 #include <cmd_confdefs.h>
169 /*set date in u-boot*/
170 #define CONFIG_RTC_M48T35A
171 #define CFG_NVRAM_BASE_ADDR 0xfc000000
172 #define CFG_NVRAM_SIZE 0x8000
174 * Miscellaneous configurable options
176 #define CONFIG_VERSION_VARIABLE 1
177 #define CONFIG_TSI108_I2C
179 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
180 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
182 #define CFG_LONGHELP /* undef to save memory */
183 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
185 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
186 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
187 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
189 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
192 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
193 #define CFG_MAXARGS 16 /* max number of command args */
194 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
196 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
197 #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
199 #define CFG_LOAD_ADDR 0x00400000 /* default load address */
201 #define CFG_HZ 1000 /* decr freq: 1ms ticks */
204 * Low Level Configuration Settings
205 * (address mappings, register initial values, etc.)
206 * You should know what you are doing if you make changes here.
209 /*-----------------------------------------------------------------------
210 * Definitions for initial stack pointer and data area
214 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
215 * To an unused memory region. The stack will remain in cache until RAM
218 #undef CFG_INIT_RAM_LOCK
219 #define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
220 #define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
222 #define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
223 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
225 /*-----------------------------------------------------------------------
226 * Start addresses for the final memory configuration
227 * (Set up by the startup code)
228 * Please note that CFG_SDRAM_BASE _must_ start at 0
231 #define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
232 #define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
234 #define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
235 #define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
237 #define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
239 #define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
241 #define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
243 #define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */
244 #define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
246 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
248 #define PCI0_IO_BASE_BOOTM 0xfd000000
250 #define CFG_RESET_ADDRESS 0x3fffff00
251 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
252 #define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */
253 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
255 /* Peripheral Device section */
258 * Resources on the Tsi108
261 #define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
262 #define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
264 #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
273 #define CONFIG_PCI /* include pci support */
274 #define CONFIG_TSI108_PCI /* include tsi108 pci support */
276 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
277 #define PCI_HOST_FORCE 1 /* configure as pci host */
278 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
280 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
281 #define CONFIG_PCI_PNP /* do pci plug-and-play */
283 /* PCI MEMORY MAP section */
285 /* PCI view of System Memory */
286 #define CFG_PCI_MEMORY_BUS 0x00000000
287 #define CFG_PCI_MEMORY_PHYS 0x00000000
288 #define CFG_PCI_MEMORY_SIZE 0x80000000
290 /* PCI Memory Space */
291 #define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
292 #define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
293 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
296 #define CFG_PCI_IO_BUS 0x00000000
297 #define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
299 #define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */
301 #define _IO_BASE 0x00000000 /* points to PCI I/O space */
303 /* PCI Config Space mapping */
304 #define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
305 #define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */
307 #define CFG_IBAT0U 0xFE0003FF
308 #define CFG_IBAT0L 0xFE000002
310 #define CFG_IBAT1U 0x00007FFF
311 #define CFG_IBAT1L 0x00000012
313 #define CFG_IBAT2U 0x80007FFF
314 #define CFG_IBAT2L 0x80000022
316 #define CFG_IBAT3U 0x00000000
317 #define CFG_IBAT3L 0x00000000
319 #define CFG_IBAT4U 0x00000000
320 #define CFG_IBAT4L 0x00000000
322 #define CFG_IBAT5U 0x00000000
323 #define CFG_IBAT5L 0x00000000
325 #define CFG_IBAT6U 0x00000000
326 #define CFG_IBAT6L 0x00000000
328 #define CFG_IBAT7U 0x00000000
329 #define CFG_IBAT7L 0x00000000
331 #define CFG_DBAT0U 0xE0003FFF
332 #define CFG_DBAT0L 0xE000002A
334 #define CFG_DBAT1U 0x00007FFF
335 #define CFG_DBAT1L 0x00000012
337 #define CFG_DBAT2U 0x00000000
338 #define CFG_DBAT2L 0x00000000
340 #define CFG_DBAT3U 0xC0000003
341 #define CFG_DBAT3L 0xC000002A
343 #define CFG_DBAT4U 0x00000000
344 #define CFG_DBAT4L 0x00000000
346 #define CFG_DBAT5U 0x00000000
347 #define CFG_DBAT5L 0x00000000
349 #define CFG_DBAT6U 0x00000000
350 #define CFG_DBAT6L 0x00000000
352 #define CFG_DBAT7U 0x00000000
353 #define CFG_DBAT7L 0x00000000
355 /* I2C addresses for the two DIMM SPD chips */
356 #define DIMM0_I2C_ADDR 0x51
357 #define DIMM1_I2C_ADDR 0x52
360 * For booting Linux, the board info and command line data
361 * have to be in the first 8 MB of memory, since this is
362 * the maximum mapped by the Linux kernel during initialization.
364 #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
366 /*-----------------------------------------------------------------------
369 #define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */
370 #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
371 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
373 #define CFG_FLASH_CFI_DRIVER
374 #define CFG_FLASH_CFI
375 #define CFG_WRITE_SWAPPED_DATA
377 #define PHYS_FLASH_SIZE 0x01000000
378 #define CFG_MAX_FLASH_SECT (128)
380 #define CFG_ENV_IS_IN_NVRAM
381 #define CFG_ENV_ADDR 0xFC000000
383 #define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
384 #define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
386 /*-----------------------------------------------------------------------
387 * Cache Configuration
389 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
390 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
391 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
394 /*-----------------------------------------------------------------------
395 * L2CR setup -- make sure this is right for your board!
396 * look in include/mpc74xx.h for the defines used here
401 #define L2_ENABLE (L2_INIT | L2CR_L2E)
404 * Internal Definitions
408 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
409 #define BOOTFLAG_WARM 0x02 /* Software reboot */
410 #define CFG_SERIAL_HANG_IN_EXCEPTION
411 #endif /* __CONFIG_H */