2 * Copyright (c) 2005 Freescale Semiconductor, Inc.
5 * Alex Bounine , Tundra Semiconductor Corp.
6 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
8 * SPDX-License-Identifier: GPL-2.0+
12 * board specific configuration options for Freescale
13 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
20 /* Board Configuration Definitions */
21 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
23 #define CONFIG_MPC7448HPC2
26 #define CONFIG_HIGH_BATS /* High BATs supported */
27 #define CONFIG_ALTIVEC /* undef to disable */
29 #define CONFIG_SYS_TEXT_BASE 0xFF000000
31 #define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
32 #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
34 #define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */
35 #define CONFIG_SYS_BUS_CLK 133000000
37 #define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
39 #undef CONFIG_ECC /* disable ECC support */
42 #include <galileo/core.h>
45 /* Board-specific Initialization Functions to be called */
46 #define CONFIG_SYS_BOARD_ASM_INIT
47 #define CONFIG_BOARD_EARLY_INIT_F
48 #define CONFIG_BOARD_EARLY_INIT_R
49 #define CONFIG_MISC_INIT_R
51 #define CONFIG_HAS_ETH0
52 #define CONFIG_HAS_ETH1
54 #define CONFIG_ENV_OVERWRITE
57 * High Level Configuration Options
61 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
63 /*#define CONFIG_SYS_HUSH_PARSER */
64 #undef CONFIG_SYS_HUSH_PARSER
67 /* Pass open firmware flat tree */
68 #define CONFIG_OF_LIBFDT 1
69 #define CONFIG_OF_BOARD_SETUP 1
71 #define OF_TSI "tsi108@c0000000"
72 #define OF_TBCLK (bd->bi_busfreq / 8)
73 #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
76 * The following defines let you select what serial you want to use
77 * for your console driver.
80 * If you have hacked a serial cable onto the second DUART channel,
81 * change the CONFIG_SYS_DUART port from 1 to 0 below.
85 #define CONFIG_CONS_INDEX 1
86 #define CONFIG_SYS_NS16550
87 #define CONFIG_SYS_NS16550_SERIAL
88 #define CONFIG_SYS_NS16550_REG_SIZE 1
89 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8
91 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
92 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
94 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
95 #define CONFIG_ZERO_BOOTDELAY_CHECK
97 #undef CONFIG_BOOTARGS
98 /* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
100 #if (CONFIG_BOOTDELAY >= 0)
101 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
102 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
103 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
105 #define CONFIG_BOOTARGS "console=ttyS0,115200"
108 #undef CONFIG_EXTRA_ENV_SETTINGS
110 #define CONFIG_SERIAL "No. 1"
112 /* Networking Configuration */
114 #define CONFIG_TSI108_ETH
115 #define CONFIG_TSI108_ETH_NUM_PORTS 2
118 #define CONFIG_BOOTFILE "zImage.initrd.elf"
119 #define CONFIG_LOADADDR 0x400000
121 /*-------------------------------------------------------------------------- */
123 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
124 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
126 #undef CONFIG_WATCHDOG /* watchdog disabled */
131 #define CONFIG_BOOTP_SUBNETMASK
132 #define CONFIG_BOOTP_GATEWAY
133 #define CONFIG_BOOTP_HOSTNAME
134 #define CONFIG_BOOTP_BOOTPATH
135 #define CONFIG_BOOTP_BOOTFILESIZE
139 * Command line configuration.
141 #include <config_cmd_default.h>
143 #define CONFIG_CMD_ASKENV
144 #define CONFIG_CMD_CACHE
145 #define CONFIG_CMD_PCI
146 #define CONFIG_CMD_I2C
147 #define CONFIG_CMD_SDRAM
148 #define CONFIG_CMD_EEPROM
149 #define CONFIG_CMD_FLASH
150 #define CONFIG_CMD_SAVEENV
151 #define CONFIG_CMD_BSP
152 #define CONFIG_CMD_DHCP
153 #define CONFIG_CMD_PING
154 #define CONFIG_CMD_DATE
157 /*set date in u-boot*/
158 #define CONFIG_RTC_M48T35A
159 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000
160 #define CONFIG_SYS_NVRAM_SIZE 0x8000
162 * Miscellaneous configurable options
164 #define CONFIG_VERSION_VARIABLE 1
165 #define CONFIG_TSI108_I2C
166 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
168 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
169 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
171 #define CONFIG_SYS_LONGHELP /* undef to save memory */
173 #if defined(CONFIG_CMD_KGDB)
174 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
175 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
177 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
181 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
182 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
184 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
185 #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
187 #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
189 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
192 * Low Level Configuration Settings
193 * (address mappings, register initial values, etc.)
194 * You should know what you are doing if you make changes here.
197 /*-----------------------------------------------------------------------
198 * Definitions for initial stack pointer and data area
202 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
203 * To an unused memory region. The stack will remain in cache until RAM
206 #undef CONFIG_SYS_INIT_RAM_LOCK
207 #define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
208 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */
210 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
212 /*-----------------------------------------------------------------------
213 * Start addresses for the final memory configuration
214 * (Set up by the startup code)
215 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
218 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
219 #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
221 #define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
222 #define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
224 #define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
226 #define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
228 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
230 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */
231 #define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
233 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
235 #define PCI0_IO_BASE_BOOTM 0xfd000000
237 #define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
238 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */
240 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
242 /* Peripheral Device section */
245 * Resources on the Tsi108
248 #define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
249 #define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
251 #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
260 #define CONFIG_PCI /* include pci support */
261 #define CONFIG_TSI108_PCI /* include tsi108 pci support */
263 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
264 #define PCI_HOST_FORCE 1 /* configure as pci host */
265 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
267 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
268 #define CONFIG_PCI_PNP /* do pci plug-and-play */
270 /* PCI MEMORY MAP section */
272 /* PCI view of System Memory */
273 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
274 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
275 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
277 /* PCI Memory Space */
278 #define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS)
279 #define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */
280 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
283 #define CONFIG_SYS_PCI_IO_BUS 0x00000000
284 #define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
286 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
288 /* PCI Config Space mapping */
289 #define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
290 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
292 #define CONFIG_SYS_IBAT0U 0xFE0003FF
293 #define CONFIG_SYS_IBAT0L 0xFE000002
295 #define CONFIG_SYS_IBAT1U 0x00007FFF
296 #define CONFIG_SYS_IBAT1L 0x00000012
298 #define CONFIG_SYS_IBAT2U 0x80007FFF
299 #define CONFIG_SYS_IBAT2L 0x80000022
301 #define CONFIG_SYS_IBAT3U 0x00000000
302 #define CONFIG_SYS_IBAT3L 0x00000000
304 #define CONFIG_SYS_IBAT4U 0x00000000
305 #define CONFIG_SYS_IBAT4L 0x00000000
307 #define CONFIG_SYS_IBAT5U 0x00000000
308 #define CONFIG_SYS_IBAT5L 0x00000000
310 #define CONFIG_SYS_IBAT6U 0x00000000
311 #define CONFIG_SYS_IBAT6L 0x00000000
313 #define CONFIG_SYS_IBAT7U 0x00000000
314 #define CONFIG_SYS_IBAT7L 0x00000000
316 #define CONFIG_SYS_DBAT0U 0xE0003FFF
317 #define CONFIG_SYS_DBAT0L 0xE000002A
319 #define CONFIG_SYS_DBAT1U 0x00007FFF
320 #define CONFIG_SYS_DBAT1L 0x00000012
322 #define CONFIG_SYS_DBAT2U 0x00000000
323 #define CONFIG_SYS_DBAT2L 0x00000000
325 #define CONFIG_SYS_DBAT3U 0xC0000003
326 #define CONFIG_SYS_DBAT3L 0xC000002A
328 #define CONFIG_SYS_DBAT4U 0x00000000
329 #define CONFIG_SYS_DBAT4L 0x00000000
331 #define CONFIG_SYS_DBAT5U 0x00000000
332 #define CONFIG_SYS_DBAT5L 0x00000000
334 #define CONFIG_SYS_DBAT6U 0x00000000
335 #define CONFIG_SYS_DBAT6L 0x00000000
337 #define CONFIG_SYS_DBAT7U 0x00000000
338 #define CONFIG_SYS_DBAT7L 0x00000000
340 /* I2C addresses for the two DIMM SPD chips */
341 #define DIMM0_I2C_ADDR 0x51
342 #define DIMM1_I2C_ADDR 0x52
345 * For booting Linux, the board info and command line data
346 * have to be in the first 8 MB of memory, since this is
347 * the maximum mapped by the Linux kernel during initialization.
349 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
351 /*-----------------------------------------------------------------------
354 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
355 #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
356 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
358 #define CONFIG_FLASH_CFI_DRIVER
359 #define CONFIG_SYS_FLASH_CFI
360 #define CONFIG_SYS_WRITE_SWAPPED_DATA
362 #define PHYS_FLASH_SIZE 0x01000000
363 #define CONFIG_SYS_MAX_FLASH_SECT (128)
365 #define CONFIG_ENV_IS_IN_NVRAM
366 #define CONFIG_ENV_ADDR 0xFC000000
368 #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
369 #define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
371 /*-----------------------------------------------------------------------
372 * Cache Configuration
374 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
375 #if defined(CONFIG_CMD_KGDB)
376 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
379 /*-----------------------------------------------------------------------
380 * L2CR setup -- make sure this is right for your board!
381 * look in include/mpc74xx.h for the defines used here
386 #define L2_ENABLE (L2_INIT | L2CR_L2E)
387 #define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
388 #endif /* __CONFIG_H */