3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
17 #define CONFIG_MPC8260 1
18 #define CONFIG_MUAS3001 1
20 #define CONFIG_SYS_TEXT_BASE 0xFF000000
22 #define CONFIG_CPM2 1 /* Has a CPM2 */
24 /* Do boardspecific init */
25 #define CONFIG_BOARD_EARLY_INIT_R 1
28 #define CONFIG_WATCHDOG 1
31 * Select serial console configuration
33 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
34 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
37 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
38 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
39 #undef CONFIG_CONS_NONE /* It's not on external UART */
40 #if defined(CONFIG_MUAS_DEV_BOARD)
41 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
43 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
47 * Select ethernet configuration
49 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
50 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
53 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
54 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
57 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
58 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
59 #undef CONFIG_ETHER_NONE /* No external Ethernet */
61 #define CONFIG_ETHER_INDEX 1
62 #define CONFIG_ETHER_ON_FCC1
63 #define CONFIG_HAS_ETH0
70 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
71 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
73 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
75 # define CONFIG_SYS_CPMFCR_RAMTYPE (0)
76 /* know on local Bus */
77 /* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
79 * - Enable Full Duplex in FSMR
81 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
83 #define CONFIG_MII /* MII PHY management */
84 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
85 # define CONFIG_SYS_PHY_ADDR 1
87 * GPIO pins used for bit-banged MII communications
89 #define MDIO_PORT 0 /* Port A */
90 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
91 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
92 #define MDC_DECLARE MDIO_DECLARE
95 #define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
96 #define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
98 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
99 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
100 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
102 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
103 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
105 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
106 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
108 #define MIIDELAY udelay(1)
110 #ifndef CONFIG_8260_CLKIN
111 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
114 #define CONFIG_BAUDRATE 115200
117 * Command line configuration.
119 #include <config_cmd_default.h>
121 #define CONFIG_CMD_DTT
122 #define CONFIG_CMD_ECHO
123 #define CONFIG_CMD_IMMAP
124 #define CONFIG_CMD_MII
125 #define CONFIG_CMD_PING
126 #define CONFIG_CMD_I2C
129 * Default environment settings
131 #define CONFIG_EXTRA_ENV_SETTINGS \
133 "u-boot_addr_r=100000\0" \
134 "kernel_addr_r=200000\0" \
135 "fdt_addr_r=400000\0" \
136 "rootpath=/opt/eldk/ppc_6xx\0" \
137 "u-boot=muas3001/u-boot.bin\0" \
138 "bootfile=muas3001/uImage\0" \
139 "fdt_file=muas3001/muas3001.dtb\0" \
140 "ramdisk_file=uRamdisk\0" \
141 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
142 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
143 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
144 "prot on ff000000 ff03ffff\0" \
145 "ramargs=setenv bootargs root=/dev/ram rw\0" \
146 "nfsargs=setenv bootargs root=/dev/nfs rw " \
147 "nfsroot=${serverip}:${rootpath}\0" \
148 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
149 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
150 "addip=setenv bootargs ${bootargs} " \
151 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
152 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
153 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
154 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
155 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
156 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
157 "tftp ${fdt_addr_r} ${fdt_file}; " \
158 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
159 "run ramargs addip; " \
160 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
161 "ramdisk_addr=ff210000\0" \
162 "kernel_addr=ff050000\0" \
163 "fdt_addr=ff200000\0" \
164 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
165 " ${ramdisk_addr} ${fdt_addr}\0" \
166 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
167 " ${ramdisk_file};" \
168 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
169 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
171 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
172 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
173 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
176 #define CONFIG_BOOTCOMMAND "run net_nfs"
177 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
180 * Miscellaneous configurable options
182 #define CONFIG_SYS_HUSH_PARSER
183 #define CONFIG_SYS_LONGHELP /* undef to save memory */
184 #if defined(CONFIG_CMD_KGDB)
185 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
187 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
190 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
193 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
194 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
196 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
198 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
202 #define CONFIG_SYS_SDRAM_BASE 0x00000000
203 #define CONFIG_SYS_FLASH_BASE 0xFF000000
204 #define CONFIG_SYS_FLASH_SIZE 32
205 #define CONFIG_SYS_FLASH_CFI
206 #define CONFIG_FLASH_CFI_DRIVER
207 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
208 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
210 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
213 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214 #define CONFIG_SYS_RAMBOOT
217 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
219 #define CONFIG_ENV_IS_IN_FLASH
221 #ifdef CONFIG_ENV_IS_IN_FLASH
222 #define CONFIG_ENV_SECT_SIZE 0x10000
223 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
224 #endif /* CONFIG_ENV_IS_IN_FLASH */
229 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
230 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
231 #define CONFIG_SYS_I2C_SLAVE 0x7F
233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
234 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
235 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
236 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
237 #define CONFIG_SYS_DTT_MAX_TEMP 70
238 #define CONFIG_SYS_DTT_LOW_TEMP -30
239 #define CONFIG_SYS_DTT_HYSTERESIS 3
241 #define CONFIG_SYS_IMMR 0xF0000000
242 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
244 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
245 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
246 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
249 /* Hard reset configuration word */
250 #define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
253 #define CONFIG_SYS_HRCW_SLAVE1 0
254 #define CONFIG_SYS_HRCW_SLAVE2 0
255 #define CONFIG_SYS_HRCW_SLAVE3 0
256 #define CONFIG_SYS_HRCW_SLAVE4 0
257 #define CONFIG_SYS_HRCW_SLAVE5 0
258 #define CONFIG_SYS_HRCW_SLAVE6 0
259 #define CONFIG_SYS_HRCW_SLAVE7 0
261 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
262 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
264 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
265 #if defined(CONFIG_CMD_KGDB)
266 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
269 #define CONFIG_SYS_HID0_INIT 0
270 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
272 #define CONFIG_SYS_HID2 0
274 #define CONFIG_SYS_SIUMCR 0x00200000
275 #define CONFIG_SYS_BCR 0x004c0000
276 #define CONFIG_SYS_SCCR 0x0
278 /*-----------------------------------------------------------------------
279 * SYPCR - System Protection Control 4-35
280 * SYPCR can only be written once after reset!
281 *-----------------------------------------------------------------------
282 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
284 #if defined(CONFIG_WATCHDOG)
285 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
286 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
288 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
289 SYPCR_SWRI|SYPCR_SWP)
290 #endif /* CONFIG_WATCHDOG */
292 /*-----------------------------------------------------------------------
293 * RMR - Reset Mode Register 5-5
294 *-----------------------------------------------------------------------
295 * turn on Checkstop Reset Enable
297 #define CONFIG_SYS_RMR 0
299 /*-----------------------------------------------------------------------
300 * TMCNTSC - Time Counter Status and Control 4-40
301 *-----------------------------------------------------------------------
302 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
303 * and enable Time Counter
305 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
307 /*-----------------------------------------------------------------------
308 * PISCR - Periodic Interrupt Status and Control 4-42
309 *-----------------------------------------------------------------------
310 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
313 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
315 /*-----------------------------------------------------------------------
316 * RCCR - RISC Controller Configuration 13-7
317 *-----------------------------------------------------------------------
319 #define CONFIG_SYS_RCCR 0
322 * Init Memory Controller:
324 * Bank Bus Machine PortSz Device
325 * ---- --- ------- ------ ------
326 * 0 60x GPCM 32 bit FLASH
327 * 1 60x SDRAM 64 bit SDRAM
328 * 4 60x GPCM 16 bit I/O Ctrl
333 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
338 #define CONFIG_SYS_OR0_PRELIM (0xff000020)
340 /* Bank 1 - 60x bus SDRAM
342 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
344 #define CONFIG_SYS_MPTPR 0x2800
346 /*-----------------------------------------------------------------------------
347 * Address for Mode Register Set (MRS) command
348 *-----------------------------------------------------------------------------
350 #define CONFIG_SYS_MRS_OFFS 0x00000110
351 #define CONFIG_SYS_PSRT 0x13
353 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
358 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
360 /* SDRAM initialization values
362 #define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
364 ORxS_ROWST_PBI1_A7 |\
367 #define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
369 #define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
371 ORxS_ROWST_PBI1_A4 |\
374 #define CONFIG_SYS_PSDMR_BIG 0x014f36a3
376 /* IO on CS4 initialization values
378 #define CONFIG_SYS_IO_BASE 0xc0000000
379 #define CONFIG_SYS_IO_SIZE 1
381 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
382 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
384 #define CONFIG_SYS_OR4_PRELIM (0xfff80020)
386 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
388 /* pass open firmware flat tree */
389 #define CONFIG_OF_LIBFDT 1
390 #define CONFIG_OF_BOARD_SETUP 1
392 #define OF_TBCLK (bd->bi_busfreq / 4)
393 #if defined(CONFIG_MUAS_DEV_BOARD)
394 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
396 #define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
399 #endif /* __CONFIG_H */