2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
9 * Configuration settings for the Freescale i.MX31 PDK board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 /* High Level Configuration Options */
34 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35 #define CONFIG_MX31 1 /* in a mx31 */
36 #define CONFIG_MX31_HCLK_FREQ 26000000
37 #define CONFIG_MX31_CLK32 32768
39 #define CONFIG_DISPLAY_CPUINFO
40 #define CONFIG_DISPLAY_BOARDINFO
42 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43 #define CONFIG_SETUP_MEMORY_TAGS 1
44 #define CONFIG_INITRD_TAG 1
46 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
47 #define CONFIG_SKIP_LOWLEVEL_INIT
48 #define CONFIG_SKIP_RELOCATE_UBOOT
51 #ifdef CONFIG_NAND_SPL
52 #define CONFIG_NAND_MXC_V1
56 * Size of malloc() pool
58 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
59 /* Bytes reserved for initial data */
60 #define CONFIG_SYS_GBL_DATA_SIZE 128
66 #define CONFIG_MXC_UART 1
67 #define CONFIG_SYS_MX31_UART1 1
69 #define CONFIG_HARD_SPI 1
70 #define CONFIG_MXC_SPI 1
71 #define CONFIG_DEFAULT_SPI_BUS 1
72 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
74 #define CONFIG_RTC_MC13783 1
76 /* MC13783 connected to CSPI2 and SS2 */
77 #define CONFIG_MC13783_SPI_BUS 1
78 #define CONFIG_MC13783_SPI_CS 2
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_CONS_INDEX 1
83 #define CONFIG_BAUDRATE 115200
84 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
86 /***********************************************************
88 ***********************************************************/
90 #include <config_cmd_default.h>
92 #define CONFIG_CMD_MII
93 #define CONFIG_CMD_PING
94 #define CONFIG_CMD_SPI
95 #define CONFIG_CMD_DATE
98 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
99 * that CFG_NO_FLASH is undefined).
101 #undef CONFIG_CMD_IMLS
103 #define CONFIG_BOOTDELAY 3
105 #define CONFIG_EXTRA_ENV_SETTINGS \
106 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
107 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
108 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
109 "bootcmd=run bootcmd_net\0" \
110 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
111 "tftpboot 0x81000000 uImage-mx31; bootm\0"
113 #define CONFIG_NET_MULTI
114 #define CONFIG_SMC911X 1
115 #define CONFIG_SMC911X_BASE 0xB6000000
116 #define CONFIG_SMC911X_32_BIT 1
119 * Miscellaneous configurable options
121 #define CONFIG_SYS_LONGHELP /* undef to save memory */
122 #define CONFIG_SYS_PROMPT "uboot> "
123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
124 /* Print Buffer Size */
125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
126 sizeof(CONFIG_SYS_PROMPT)+16)
127 /* max number of command args */
128 #define CONFIG_SYS_MAXARGS 16
129 /* Boot Argument Buffer Size */
130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
132 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_START 0x80000000
134 #define CONFIG_SYS_MEMTEST_END 0x10000
136 /* default load address */
137 #define CONFIG_SYS_LOAD_ADDR 0x81000000
139 #define CONFIG_SYS_HZ 1000
141 #define CONFIG_CMDLINE_EDITING 1
143 /*-----------------------------------------------------------------------
146 * The stack sizes are set up in start.S using the settings below
148 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
150 /*-----------------------------------------------------------------------
151 * Physical Memory Map
153 #define CONFIG_NR_DRAM_BANKS 1
154 #define PHYS_SDRAM_1 CSD0_BASE
155 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
157 /*-----------------------------------------------------------------------
158 * FLASH and environment organization
160 /* No NOR flash present */
161 #define CONFIG_SYS_NO_FLASH 1
163 #define CONFIG_ENV_IS_NOWHERE 1
165 #define CONFIG_ENV_SIZE (128 * 1024)
167 /* NAND configuration for the NAND_SPL */
169 /* Start copying real U-boot from the second page */
170 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
171 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
172 /* Load U-Boot to this address */
173 #define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
174 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
176 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
177 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
178 #define CONFIG_SYS_NAND_PAGE_COUNT 64
179 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
180 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
183 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
184 #define CCM_CCMR_SETUP 0x074B0BF5
185 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
186 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
187 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
189 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
192 #define ESDMISC_MDDR_SETUP 0x00000004
193 #define ESDMISC_MDDR_RESET_DL 0x0000000c
194 #define ESDCFG0_MDDR_SETUP 0x006ac73a
196 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
197 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
198 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
199 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
200 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
201 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
202 #define ESDCTL_RW ESDCTL_SETTINGS
204 #endif /* __CONFIG_H */