1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Kshitij Gupta <kshitij@ti.com>
10 * Configuration settings for the Freescale i.MX31 PDK board.
16 #include <asm/arch/imx-regs.h>
18 /* High Level Configuration Options */
19 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
20 #define CONFIG_SETUP_MEMORY_TAGS
21 #define CONFIG_INITRD_TAG
23 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SPL_MAX_SIZE 2048
28 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
30 #ifndef CONFIG_SPL_BUILD
31 #define CONFIG_SKIP_LOWLEVEL_INIT
35 * Size of malloc() pool
37 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
43 #define CONFIG_MXC_UART
44 #define CONFIG_MXC_UART_BASE UART1_BASE
46 #define CONFIG_HARD_SPI
47 #define CONFIG_DEFAULT_SPI_BUS 1
48 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
52 #define CONFIG_POWER_SPI
53 #define CONFIG_POWER_FSL
54 #define CONFIG_FSL_PMIC_BUS 1
55 #define CONFIG_FSL_PMIC_CS 2
56 #define CONFIG_FSL_PMIC_CLK 1000000
57 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
58 #define CONFIG_FSL_PMIC_BITLEN 32
59 #define CONFIG_RTC_MC13XXX
61 /* allow to overwrite serial and ethaddr */
62 #define CONFIG_ENV_OVERWRITE
64 #define CONFIG_EXTRA_ENV_SETTINGS \
65 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
66 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
67 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
68 "bootcmd=run bootcmd_net\0" \
69 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
70 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
71 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
72 "nand erase 0x0 0x40000; " \
73 "nand write 0x81000000 0x0 0x40000\0"
76 * Miscellaneous configurable options
79 /* memtest works on */
80 #define CONFIG_SYS_MEMTEST_START 0x80000000
81 #define CONFIG_SYS_MEMTEST_END 0x80010000
83 /* default load address */
84 #define CONFIG_SYS_LOAD_ADDR 0x81000000
86 /*-----------------------------------------------------------------------
89 #define CONFIG_NR_DRAM_BANKS 1
90 #define PHYS_SDRAM_1 CSD0_BASE
91 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
93 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
94 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
95 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
96 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
97 GENERATED_GBL_DATA_SIZE)
98 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
99 CONFIG_SYS_INIT_RAM_SIZE)
102 * environment organization
104 #define CONFIG_ENV_OFFSET 0x40000
105 #define CONFIG_ENV_OFFSET_REDUND 0x60000
106 #define CONFIG_ENV_SIZE (128 * 1024)
111 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
112 #define CONFIG_SYS_MAX_NAND_DEVICE 1
113 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
114 #define CONFIG_MXC_NAND_HWECC
115 #define CONFIG_SYS_NAND_LARGEPAGE
117 /* NAND configuration for the NAND_SPL */
119 /* Start copying real U-Boot from the second page */
120 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
121 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
122 /* Load U-Boot to this address */
123 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
124 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
126 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
127 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
128 #define CONFIG_SYS_NAND_PAGE_COUNT 64
129 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
130 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
132 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
133 #define CCM_CCMR_SETUP 0x074B0BF5
134 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
135 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
136 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
137 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
138 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
141 #define ESDMISC_MDDR_SETUP 0x00000004
142 #define ESDMISC_MDDR_RESET_DL 0x0000000c
143 #define ESDCFG0_MDDR_SETUP 0x006ac73a
145 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
146 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
147 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
148 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
149 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
150 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
151 #define ESDCTL_RW ESDCTL_SETTINGS
153 #endif /* __CONFIG_H */