2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
9 * Configuration settings for the Freescale i.MX31 PDK board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/imx-regs.h>
19 /* High Level Configuration Options */
20 #define CONFIG_MX31 /* This is a mx31 */
22 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23 #define CONFIG_SETUP_MEMORY_TAGS
24 #define CONFIG_INITRD_TAG
26 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29 #define CONFIG_SPL_MAX_SIZE 2048
31 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
32 #define CONFIG_SYS_TEXT_BASE 0x87e00000
34 #ifndef CONFIG_SPL_BUILD
35 #define CONFIG_SKIP_LOWLEVEL_INIT
39 * Size of malloc() pool
41 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
47 #define CONFIG_MXC_UART
48 #define CONFIG_MXC_UART_BASE UART1_BASE
50 #define CONFIG_HARD_SPI
51 #define CONFIG_MXC_SPI
52 #define CONFIG_DEFAULT_SPI_BUS 1
53 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
57 #define CONFIG_POWER_SPI
58 #define CONFIG_POWER_FSL
59 #define CONFIG_FSL_PMIC_BUS 1
60 #define CONFIG_FSL_PMIC_CS 2
61 #define CONFIG_FSL_PMIC_CLK 1000000
62 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
63 #define CONFIG_FSL_PMIC_BITLEN 32
64 #define CONFIG_RTC_MC13XXX
66 /* allow to overwrite serial and ethaddr */
67 #define CONFIG_ENV_OVERWRITE
68 #define CONFIG_CONS_INDEX 1
70 #define CONFIG_EXTRA_ENV_SETTINGS \
71 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
72 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
73 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
74 "bootcmd=run bootcmd_net\0" \
75 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
76 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
77 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
78 "nand erase 0x0 0x40000; " \
79 "nand write 0x81000000 0x0 0x40000\0"
82 * Miscellaneous configurable options
84 #define CONFIG_SYS_LONGHELP /* undef to save memory */
86 /* memtest works on */
87 #define CONFIG_SYS_MEMTEST_START 0x80000000
88 #define CONFIG_SYS_MEMTEST_END 0x80010000
90 /* default load address */
91 #define CONFIG_SYS_LOAD_ADDR 0x81000000
93 #define CONFIG_CMDLINE_EDITING
95 /*-----------------------------------------------------------------------
98 #define CONFIG_NR_DRAM_BANKS 1
99 #define PHYS_SDRAM_1 CSD0_BASE
100 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
102 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
103 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
104 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
105 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
106 GENERATED_GBL_DATA_SIZE)
107 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
108 CONFIG_SYS_INIT_RAM_SIZE)
111 * environment organization
113 #define CONFIG_ENV_OFFSET 0x40000
114 #define CONFIG_ENV_OFFSET_REDUND 0x60000
115 #define CONFIG_ENV_SIZE (128 * 1024)
120 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
121 #define CONFIG_SYS_MAX_NAND_DEVICE 1
122 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
123 #define CONFIG_MXC_NAND_HWECC
124 #define CONFIG_SYS_NAND_LARGEPAGE
126 /* NAND configuration for the NAND_SPL */
128 /* Start copying real U-Boot from the second page */
129 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
130 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
131 /* Load U-Boot to this address */
132 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
133 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
135 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
136 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
137 #define CONFIG_SYS_NAND_PAGE_COUNT 64
138 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
139 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
141 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
142 #define CCM_CCMR_SETUP 0x074B0BF5
143 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
144 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
145 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
146 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
147 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
150 #define ESDMISC_MDDR_SETUP 0x00000004
151 #define ESDMISC_MDDR_RESET_DL 0x0000000c
152 #define ESDCFG0_MDDR_SETUP 0x006ac73a
154 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
155 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
156 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
157 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
158 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
159 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
160 #define ESDCTL_RW ESDCTL_SETTINGS
162 #endif /* __CONFIG_H */