2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Configuration settings for the MX53SMD Freescale board.
6 * SPDX-License-Identifier: GPL-2.0+
14 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
16 #include <asm/arch/imx-regs.h>
18 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
19 #define CONFIG_SETUP_MEMORY_TAGS
20 #define CONFIG_INITRD_TAG
21 #define CONFIG_REVISION_TAG
23 #define CONFIG_SYS_FSL_CLK
25 /* Size of malloc() pool */
26 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
28 #define CONFIG_BOARD_EARLY_INIT_F
29 #define CONFIG_MXC_GPIO
31 #define CONFIG_MXC_UART
32 #define CONFIG_MXC_UART_BASE UART1_BASE
35 #define CONFIG_SYS_I2C
36 #define CONFIG_SYS_I2C_MXC
37 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
38 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
39 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
42 #define CONFIG_FSL_ESDHC
43 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
44 #define CONFIG_SYS_FSL_ESDHC_NUM 1
47 #define CONFIG_GENERIC_MMC
48 #define CONFIG_DOS_PARTITION
51 #define CONFIG_HAS_ETH1
54 #define CONFIG_FEC_MXC
55 #define IMX_FEC_BASE FEC_BASE_ADDR
56 #define CONFIG_FEC_MXC_PHYADDR 0x1F
58 /* allow to overwrite serial and ethaddr */
59 #define CONFIG_ENV_OVERWRITE
60 #define CONFIG_CONS_INDEX 1
61 #define CONFIG_BAUDRATE 115200
63 /* Command definition */
65 #define CONFIG_ETHPRIME "FEC0"
67 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
68 #define CONFIG_SYS_TEXT_BASE 0x77800000
70 #define CONFIG_EXTRA_ENV_SETTINGS \
75 "mmcroot=/dev/mmcblk0p3 rw\0" \
76 "mmcrootfstype=ext3 rootwait\0" \
77 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
79 "rootfstype=${mmcrootfstype}\0" \
81 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
82 "bootscript=echo Running bootscript from mmc ...; " \
84 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
85 "mmcboot=echo Booting from mmc ...; " \
88 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
90 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
91 "netboot=echo Booting from net ...; " \
93 "dhcp ${uimage}; bootm\0" \
95 #define CONFIG_BOOTCOMMAND \
96 "mmc dev ${mmcdev}; if mmc rescan; then " \
97 "if run loadbootscript; then " \
100 "if run loaduimage; then " \
102 "else run netboot; " \
105 "else run netboot; fi"
106 #define CONFIG_ARP_TIMEOUT 200UL
108 /* Miscellaneous configurable options */
109 #define CONFIG_SYS_LONGHELP /* undef to save memory */
110 #define CONFIG_AUTO_COMPLETE
111 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
113 /* Print Buffer Size */
114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
115 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
118 #define CONFIG_SYS_MEMTEST_START 0x70000000
119 #define CONFIG_SYS_MEMTEST_END 0x70010000
121 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
123 #define CONFIG_CMDLINE_EDITING
125 /* Physical Memory Map */
126 #define CONFIG_NR_DRAM_BANKS 2
127 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
128 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
129 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
130 #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
131 #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
133 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
134 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
135 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
137 #define CONFIG_SYS_INIT_SP_OFFSET \
138 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
139 #define CONFIG_SYS_INIT_SP_ADDR \
140 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
142 /* FLASH and environment organization */
143 #define CONFIG_SYS_NO_FLASH
145 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
146 #define CONFIG_ENV_SIZE (8 * 1024)
147 #define CONFIG_ENV_IS_IN_MMC
148 #define CONFIG_SYS_MMC_ENV_DEV 0
150 #endif /* __CONFIG_H */