2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 #define CONFIG_SPL_LIBCOMMON_SUPPORT
17 #define CONFIG_SPL_MMC_SUPPORT
21 /* Size of malloc() pool */
22 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
24 #define CONFIG_BOARD_EARLY_INIT_F
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE UART1_BASE
29 #define CONFIG_EXTRA_ENV_SETTINGS \
33 "fdt_high=0xffffffff\0" \
34 "initrd_high=0xffffffff\0" \
35 "fdt_file=imx6sx-sdb.dtb\0" \
36 "fdt_addr=0x88000000\0" \
41 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
42 "mmcargs=setenv bootargs console=${console},${baudrate} " \
45 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
46 "bootscript=echo Running bootscript from mmc ...; " \
48 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
49 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
50 "mmcboot=echo Booting from mmc ...; " \
52 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
53 "if run loadfdt; then " \
54 "bootz ${loadaddr} - ${fdt_addr}; " \
56 "if test ${boot_fdt} = try; then " \
59 "echo WARN: Cannot load the DT; " \
65 "netargs=setenv bootargs console=${console},${baudrate} " \
67 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
68 "netboot=echo Booting from net ...; " \
70 "if test ${ip_dyn} = yes; then " \
71 "setenv get_cmd dhcp; " \
73 "setenv get_cmd tftp; " \
75 "${get_cmd} ${image}; " \
76 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
77 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
78 "bootz ${loadaddr} - ${fdt_addr}; " \
80 "if test ${boot_fdt} = try; then " \
83 "echo WARN: Cannot load the DT; " \
90 #define CONFIG_BOOTCOMMAND \
91 "mmc dev ${mmcdev};" \
92 "mmc dev ${mmcdev}; if mmc rescan; then " \
93 "if run loadbootscript; then " \
96 "if run loadimage; then " \
98 "else run netboot; " \
101 "else run netboot; fi"
103 /* Miscellaneous configurable options */
104 #define CONFIG_SYS_MEMTEST_START 0x80000000
105 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
107 #define CONFIG_STACKSIZE SZ_128K
109 /* Physical Memory Map */
110 #define CONFIG_NR_DRAM_BANKS 1
111 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
112 #define PHYS_SDRAM_SIZE SZ_1G
114 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
115 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
116 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
118 #define CONFIG_SYS_INIT_SP_OFFSET \
119 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
120 #define CONFIG_SYS_INIT_SP_ADDR \
121 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
123 /* MMC Configuration */
124 #define CONFIG_FSL_ESDHC
125 #define CONFIG_FSL_USDHC
126 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
129 #define CONFIG_CMD_MMC
130 #define CONFIG_GENERIC_MMC
131 #define CONFIG_BOUNCE_BUFFER
132 #define CONFIG_CMD_EXT2
133 #define CONFIG_CMD_FAT
134 #define CONFIG_DOS_PARTITION
137 #define CONFIG_CMD_I2C
138 #define CONFIG_SYS_I2C
139 #define CONFIG_SYS_I2C_MXC
140 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
141 #define CONFIG_SYS_I2C_SPEED 100000
145 #define CONFIG_POWER_I2C
146 #define CONFIG_POWER_PFUZE100
147 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
150 #define CONFIG_CMD_PING
151 #define CONFIG_CMD_DHCP
152 #define CONFIG_CMD_MII
153 #define CONFIG_CMD_NET
154 #define CONFIG_FEC_MXC
157 #define IMX_FEC_BASE ENET_BASE_ADDR
158 #define CONFIG_FEC_MXC_PHYADDR 0x1
160 #define CONFIG_FEC_XCV_TYPE RGMII
161 #define CONFIG_ETHPRIME "FEC"
163 #define CONFIG_PHYLIB
164 #define CONFIG_PHY_ATHEROS
167 #define CONFIG_CMD_USB
168 #ifdef CONFIG_CMD_USB
169 #define CONFIG_USB_EHCI
170 #define CONFIG_USB_EHCI_MX6
171 #define CONFIG_USB_STORAGE
172 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
173 #define CONFIG_USB_HOST_ETHER
174 #define CONFIG_USB_ETHER_ASIX
175 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
176 #define CONFIG_MXC_USB_FLAGS 0
177 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
180 #define CONFIG_CMD_PCI
181 #ifdef CONFIG_CMD_PCI
183 #define CONFIG_PCI_PNP
184 #define CONFIG_PCI_SCAN_SHOW
185 #define CONFIG_PCIE_IMX
186 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
187 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
190 #define CONFIG_IMX6_THERMAL
192 #define CONFIG_CMD_FUSE
193 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
194 #define CONFIG_MXC_OCOTP
197 #define CONFIG_CMD_TIME
199 #define CONFIG_FSL_QSPI
201 #ifdef CONFIG_FSL_QSPI
202 #define CONFIG_CMD_SF
203 #define CONFIG_SPI_FLASH
204 #define CONFIG_SPI_FLASH_BAR
205 #define CONFIG_SPI_FLASH_SPANSION
206 #define CONFIG_SPI_FLASH_STMICRO
207 #define CONFIG_SYS_FSL_QSPI_LE
208 #define CONFIG_SYS_FSL_QSPI_AHB
209 #ifdef CONFIG_MX6SX_SABRESD_REVA
210 #define FSL_QSPI_FLASH_SIZE SZ_16M
212 #define FSL_QSPI_FLASH_SIZE SZ_32M
214 #define FSL_QSPI_FLASH_NUM 2
217 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
218 #define CONFIG_ENV_SIZE SZ_8K
219 #define CONFIG_ENV_IS_IN_MMC
221 #define CONFIG_OF_LIBFDT
222 #define CONFIG_CMD_BOOTZ
224 #ifndef CONFIG_SYS_DCACHE_OFF
225 #define CONFIG_CMD_CACHE
228 #define CONFIG_SYS_FSL_USDHC_NUM 3
229 #if defined(CONFIG_ENV_IS_IN_MMC)
230 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
233 #endif /* __CONFIG_H */