2 * Common configuration options for ifm camera boards
5 * Sebastien Cazaux, ifm electronic gmbh
8 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __O2D_CONFIG_H
14 #define __O2D_CONFIG_H
17 * High Level Configuration Options
19 #define CONFIG_MPC5200
21 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
23 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
24 #if defined(CONFIG_CMD_KGDB)
25 /* log base 2 of the above value */
26 #define CONFIG_SYS_CACHELINE_SHIFT 5
30 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
35 /* preserve space for the post_word at end of on-chip SRAM */
36 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
40 * Serial console configuration
42 #define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
43 #define CONFIG_SYS_BAUDRATE_TABLE \
44 { 9600, 19200, 38400, 57600, 115200, 230400 }
48 * 0x40000000 - 0x4fffffff - PCI Memory
49 * 0x50000000 - 0x50ffffff - PCI IO Space
52 #define CONFIG_PCI_MEM_BUS 0x40000000
53 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
54 #define CONFIG_PCI_MEM_SIZE 0x10000000
56 #define CONFIG_PCI_IO_BUS 0x50000000
57 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
58 #define CONFIG_PCI_IO_SIZE 0x01000000
60 #define CONFIG_SYS_XLB_PIPELINING 1
64 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
66 #define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
72 #define CONFIG_CMD_PCI
75 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
76 /* Boot low with 16 or 32 MB Flash */
77 #define CONFIG_SYS_LOWBOOT 1
78 #elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
79 #error "CONFIG_SYS_TEXT_BASE value is invalid"
83 #define CONFIG_PREBOOT "run master"
85 #undef CONFIG_BOOTARGS
87 #if !defined(CONSOLE_DEV)
88 #define CONSOLE_DEV "ttyPSC1"
92 * Default environment for booting old and new kernel versions
94 #define CONFIG_IFM_DEFAULT_ENV_OLD \
95 "flash_self_old=run ramargs addip addmem;" \
96 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
97 "flash_nfs_old=run nfsargs addip addmem;" \
98 "bootm ${kernel_addr}\0" \
99 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
100 "run nfsargs addip addmem;" \
101 "bootm ${kernel_addr_r}\0"
103 #define CONFIG_IFM_DEFAULT_ENV_NEW \
104 "fdt_addr_r=900000\0" \
105 "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
106 "flash_self=run ramargs addip addtty addmisc;" \
107 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
108 "flash_nfs=run nfsargs addip addtty addmisc;" \
109 "bootm ${kernel_addr} - ${fdt_addr}\0" \
110 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
111 "tftp ${fdt_addr_r} ${fdt_file}; " \
112 "run nfsargs addip addtty addmisc;" \
113 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
115 #define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
117 "addip=setenv bootargs ${bootargs} " \
118 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
119 ":${hostname}:${netdev}:off panic=1\0" \
120 "addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
121 "addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
122 "addtty=sete bootargs ${bootargs} console=" \
123 CONSOLE_DEV ",${baudrate}\0" \
124 "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
125 "kernel_addr_r=600000\0" \
126 "initrd_high=0x03e00000\0" \
127 "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
128 "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
130 "nfsargs=setenv bootargs root=/dev/nfs rw " \
131 "nfsroot=${serverip}:${rootpath}\0" \
132 "ramargs=setenv bootargs root=/dev/ram rw\0" \
133 "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
134 "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
135 "cp.b ${fileaddr} ${linbot} ${filesize}\0" \
136 "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
137 "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
138 "cp.b ${fileaddr} ${rambot} ${filesize}\0" \
139 "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
140 "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
141 "cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
142 "rootpath=/opt/eldk/ppc_6xx\0" \
143 "uboname=" CONFIG_BOARD_NAME \
144 "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
145 "progubo=tftp 200000 ${uboname};" \
146 "protect off ${ubobot} ${ubotop};" \
147 "erase ${ubobot} ${ubotop};" \
148 "cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
150 "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
151 "setenv bootdelay 1;" \
152 "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \
153 BOARD_POST_CRC32_END";" \
154 "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
156 #define CONFIG_BOOTCOMMAND "run post"
159 * IPB Bus clocking configuration.
161 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
163 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
165 * PCI Bus clocking configuration
167 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
168 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
169 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
171 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
175 * There is no write delay with FRAM, write operations are performed at bus
176 * speed. Thus, no status polling or write delay is needed.
180 * Flash configuration
182 #define CONFIG_SYS_FLASH_CFI 1
183 #define CONFIG_FLASH_CFI_DRIVER 1
184 #define CONFIG_FLASH_16BIT
185 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
186 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
187 #define CONFIG_SYS_FLASH_EMPTY_INFO
189 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
190 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
191 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
193 /* Timeout for Flash Clear Lock Bits (in ms) */
194 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
195 /* "Real" (hardware) sectors protection */
196 #define CONFIG_SYS_FLASH_PROTECTION
199 * Environment settings
201 #define CONFIG_ENV_IS_IN_FLASH 1
202 #define CONFIG_ENV_SIZE 0x20000
203 #define CONFIG_ENV_SECT_SIZE 0x20000
204 #define CONFIG_ENV_OVERWRITE 1
205 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
210 #define CONFIG_SYS_MBAR 0xF0000000
211 #define CONFIG_SYS_SDRAM_BASE 0x00000000
212 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
214 /* Use SRAM until RAM will be available */
215 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
217 /* preserve space for the post_word at end of on-chip SRAM */
218 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
220 /* End of used area in DPRAM */
221 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
224 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
225 GENERATED_GBL_DATA_SIZE)
226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
229 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
230 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
231 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
233 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
234 #define CONFIG_SYS_RAMBOOT 1
238 * Ethernet configuration
240 #define CONFIG_MPC5xxx_FEC
241 #define CONFIG_MPC5xxx_FEC_MII100
242 #define CONFIG_PHY_ADDR 0x00
243 #define CONFIG_RESET_PHY_R
248 #define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
249 #define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
250 #define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
251 #define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
254 * Miscellaneous configurable options
256 #define CONFIG_SYS_LONGHELP /* undef to save memory */
257 #define CONFIG_CMDLINE_EDITING
259 #if defined(CONFIG_CMD_KGDB)
260 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
262 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
264 /* Print Buffer Size */
265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
266 sizeof(CONFIG_SYS_PROMPT) + 16)
267 /* max number of command args */
268 #define CONFIG_SYS_MAXARGS 16
269 /* Boot Argument Buffer Size */
270 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
272 /* default load address */
273 #define CONFIG_SYS_LOAD_ADDR 0x100000
275 /* decrementer freq: 1 ms ticks */
278 * Various low-level settings
280 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
281 #define CONFIG_SYS_HID0_FINAL HID0_ICE
283 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
284 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
285 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
286 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
288 #define CONFIG_BOARD_EARLY_INIT_R
290 #define CONFIG_SYS_CS_BURST 0x00000000
291 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
296 #define OF_CPU "PowerPC,5200@0"
297 #define OF_SOC "soc5200@f0000000"
298 #define OF_TBCLK (bd->bi_busfreq / 4)
300 #endif /* __O2D_CONFIG_H */