2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
34 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
35 #define CONFIG_OMAP 1 /* in a TI OMAP core */
36 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
37 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
38 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
40 #define CONFIG_SDRC /* The chip has SDRC controller */
42 #include <asm/arch/cpu.h> /* get chip and board defs */
43 #include <asm/arch/omap3.h>
46 * Display CPU and Board information
48 #define CONFIG_DISPLAY_CPUINFO 1
49 #define CONFIG_DISPLAY_BOARDINFO 1
52 #define V_OSCK 26000000 /* Clock output from T2 */
53 #define V_SCLK (V_OSCK >> 1)
55 #undef CONFIG_USE_IRQ /* no support for IRQs */
56 #define CONFIG_MISC_INIT_R
58 #define CONFIG_OF_LIBFDT 1
60 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
61 #define CONFIG_SETUP_MEMORY_TAGS 1
62 #define CONFIG_INITRD_TAG 1
63 #define CONFIG_REVISION_TAG 1
66 * Size of malloc() pool
68 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
70 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
78 * NS16550 Configuration
80 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
82 #define CONFIG_SYS_NS16550
83 #define CONFIG_SYS_NS16550_SERIAL
84 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
85 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
88 * select serial console configuration
90 #define CONFIG_CONS_INDEX 3
91 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
92 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
94 /* allow to overwrite serial and ethaddr */
95 #define CONFIG_ENV_OVERWRITE
96 #define CONFIG_BAUDRATE 115200
97 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
99 #define CONFIG_GENERIC_MMC 1
101 #define CONFIG_OMAP_HSMMC 1
102 #define CONFIG_DOS_PARTITION 1
104 /* DDR - I use Micron DDR */
105 #define CONFIG_OMAP3_MICRON_DDR 1
108 #define CONFIG_MUSB_UDC 1
109 #define CONFIG_USB_OMAP3 1
110 #define CONFIG_TWL4030_USB 1
112 /* USB device configuration */
113 #define CONFIG_USB_DEVICE 1
114 #define CONFIG_USB_TTY 1
115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
117 /* commands to include */
118 #include <config_cmd_default.h>
120 #define CONFIG_CMD_CACHE
121 #define CONFIG_CMD_EXT2 /* EXT2 Support */
122 #define CONFIG_CMD_FAT /* FAT support */
123 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
124 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
125 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
126 #define MTDIDS_DEFAULT "nand0=nand"
127 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
128 "1920k(u-boot),128k(u-boot-env),"\
131 #define CONFIG_CMD_I2C /* I2C serial bus support */
132 #define CONFIG_CMD_MMC /* MMC support */
133 #define CONFIG_CMD_NAND /* NAND support */
135 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
136 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
137 #undef CONFIG_CMD_IMI /* iminfo */
138 #undef CONFIG_CMD_IMLS /* List all found images */
139 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
140 #undef CONFIG_CMD_NFS /* NFS support */
142 #define CONFIG_SYS_NO_FLASH
143 #define CONFIG_HARD_I2C 1
144 #define CONFIG_SYS_I2C_SPEED 100000
145 #define CONFIG_SYS_I2C_SLAVE 1
146 #define CONFIG_SYS_I2C_BUS 0
147 #define CONFIG_SYS_I2C_BUS_SELECT 1
148 #define CONFIG_I2C_MULTI_BUS 1
149 #define CONFIG_DRIVER_OMAP34XX_I2C 1
154 #define CONFIG_TWL4030_POWER 1
155 #define CONFIG_TWL4030_LED 1
160 #define CONFIG_SYS_NAND_QUIET_TEST 1
161 #define CONFIG_NAND_OMAP_GPMC
162 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
164 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
165 /* to access nand at */
167 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
171 #define CONFIG_JFFS2_NAND
172 /* nand device jffs2 lives on */
173 #define CONFIG_JFFS2_DEV "nand0"
174 /* start of jffs2 partition */
175 #define CONFIG_JFFS2_PART_OFFSET 0x680000
176 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
179 /* Environment information */
180 #define CONFIG_BOOTDELAY 10
182 #define CONFIG_EXTRA_ENV_SETTINGS \
183 "loadaddr=0x82000000\0" \
185 "console=ttyS2,115200n8\0" \
188 "dvimode=1024x768MR-16@60\0" \
189 "defaultdisplay=dvi\0" \
191 "mmcroot=/dev/mmcblk0p2 rw\0" \
192 "mmcrootfstype=ext3 rootwait\0" \
193 "nandroot=/dev/mtdblock4 rw\0" \
194 "nandrootfstype=jffs2\0" \
195 "mmcargs=setenv bootargs console=${console} " \
196 "mpurate=${mpurate} " \
198 "omapfb.mode=dvi:${dvimode} " \
200 "omapdss.def_disp=${defaultdisplay} " \
202 "rootfstype=${mmcrootfstype}\0" \
203 "nandargs=setenv bootargs console=${console} " \
204 "mpurate=${mpurate} " \
206 "omapfb.mode=dvi:${dvimode} " \
208 "omapdss.def_disp=${defaultdisplay} " \
209 "root=${nandroot} " \
210 "rootfstype=${nandrootfstype}\0" \
211 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
212 "bootscript=echo Running bootscript from mmc ...; " \
213 "source ${loadaddr}\0" \
214 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
215 "mmcboot=echo Booting from mmc ...; " \
217 "bootm ${loadaddr}\0" \
218 "nandboot=echo Booting from nand ...; " \
220 "nand read ${loadaddr} 280000 400000; " \
221 "bootm ${loadaddr}\0" \
223 #define CONFIG_BOOTCOMMAND \
224 "if mmc rescan ${mmcdev}; then " \
225 "if run loadbootscript; then " \
228 "if run loaduimage; then " \
230 "else run nandboot; " \
233 "else run nandboot; fi"
235 #define CONFIG_AUTO_COMPLETE 1
237 * Miscellaneous configurable options
239 #define CONFIG_SYS_LONGHELP /* undef to save memory */
240 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
241 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
242 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
243 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
244 /* Print Buffer Size */
245 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
246 sizeof(CONFIG_SYS_PROMPT) + 16)
247 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
248 /* Boot Argument Buffer Size */
249 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
251 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
253 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
254 0x01F00000) /* 31MB */
256 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
260 * OMAP3 has 12 GP timers, they can be driven by the system clock
261 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
262 * This rate is divided by a local divisor.
264 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
265 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
266 #define CONFIG_SYS_HZ 1000
268 /*-----------------------------------------------------------------------
271 * The stack sizes are set up in start.S using the settings below
273 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
274 #ifdef CONFIG_USE_IRQ
275 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
276 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
279 /*-----------------------------------------------------------------------
280 * Physical Memory Map
282 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
283 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
284 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
285 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
287 /* SDRAM Bank Allocation method */
290 /*-----------------------------------------------------------------------
291 * FLASH and environment organization
294 /* **** PISMO SUPPORT *** */
296 /* Configure the PISMO */
297 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
298 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
300 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
302 #define CONFIG_SYS_FLASH_BASE boot_flash_base
304 /* Monitor at start of flash */
305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
306 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
308 #define CONFIG_ENV_IS_IN_NAND 1
309 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
310 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
312 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
313 #define CONFIG_ENV_OFFSET boot_flash_off
314 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
317 extern unsigned int boot_flash_base;
318 extern volatile unsigned int boot_flash_env_addr;
319 extern unsigned int boot_flash_off;
320 extern unsigned int boot_flash_sec;
321 extern unsigned int boot_flash_type;
324 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
325 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
326 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
327 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
328 CONFIG_SYS_INIT_RAM_SIZE - \
329 GENERATED_GBL_DATA_SIZE)
331 #define CONFIG_OMAP3_SPI
333 #endif /* __CONFIG_H */