2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * SPDX-License-Identifier: GPL-2.0+
16 * High Level Configuration Options
18 #define CONFIG_OMAP 1 /* in a TI OMAP core */
19 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
20 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
21 #define CONFIG_OMAP_GPIO
22 #define CONFIG_OMAP_COMMON
24 #define CONFIG_SDRC /* The chip has SDRC controller */
26 #include <asm/arch/cpu.h> /* get chip and board defs */
27 #include <asm/arch/omap3.h>
30 * Display CPU and Board information
32 #define CONFIG_DISPLAY_CPUINFO 1
33 #define CONFIG_DISPLAY_BOARDINFO 1
36 #define V_OSCK 26000000 /* Clock output from T2 */
37 #define V_SCLK (V_OSCK >> 1)
39 #define CONFIG_MISC_INIT_R
41 #define CONFIG_OF_LIBFDT
42 #define CONFIG_CMD_BOOTZ
44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS 1
46 #define CONFIG_INITRD_TAG 1
47 #define CONFIG_REVISION_TAG 1
50 * Size of malloc() pool
52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
61 * NS16550 Configuration
63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
65 #define CONFIG_SYS_NS16550
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
71 * select serial console configuration
73 #define CONFIG_CONS_INDEX 3
74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
75 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 #define CONFIG_GENERIC_MMC 1
84 #define CONFIG_OMAP_HSMMC 1
85 #define CONFIG_DOS_PARTITION 1
88 #define CONFIG_STATUS_LED 1
89 #define CONFIG_BOARD_SPECIFIC_LED 1
90 #define STATUS_LED_BIT 0x01
91 #define STATUS_LED_STATE STATUS_LED_ON
92 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
93 #define STATUS_LED_BIT1 0x02
94 #define STATUS_LED_STATE1 STATUS_LED_ON
95 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
96 #define STATUS_LED_BOOT STATUS_LED_BIT
97 #define STATUS_LED_GREEN STATUS_LED_BIT1
99 /* Enable Multi Bus support for I2C */
100 #define CONFIG_I2C_MULTI_BUS 1
102 /* Probe all devices */
103 #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
106 #define CONFIG_MUSB_GADGET
107 #define CONFIG_USB_MUSB_OMAP2PLUS
108 #define CONFIG_MUSB_PIO_ONLY
109 #define CONFIG_USB_GADGET_DUALSPEED
110 #define CONFIG_TWL4030_USB 1
111 #define CONFIG_USB_ETHER
112 #define CONFIG_USB_ETHER_RNDIS
115 #define CONFIG_CMD_USB
116 #define CONFIG_USB_EHCI
118 #define CONFIG_USB_EHCI_OMAP
119 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
121 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
122 #define CONFIG_USB_HOST_ETHER
123 #define CONFIG_USB_ETHER_SMSC95XX
124 #define CONFIG_USB_ETHER_ASIX
127 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
128 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
130 /* commands to include */
131 #include <config_cmd_default.h>
133 #define CONFIG_CMD_ASKENV
135 #define CONFIG_CMD_CACHE
136 #define CONFIG_CMD_EXT2 /* EXT2 Support */
137 #define CONFIG_CMD_FAT /* FAT support */
138 #define CONFIG_CMD_FS_GENERIC /* Generic FS support */
139 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
140 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
141 #define MTDIDS_DEFAULT "nand0=nand"
142 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
143 "1920k(u-boot),128k(u-boot-env),"\
146 #define CONFIG_CMD_I2C /* I2C serial bus support */
147 #define CONFIG_CMD_MMC /* MMC support */
148 #define CONFIG_USB_STORAGE /* USB storage support */
149 #define CONFIG_CMD_NAND /* NAND support */
150 #define CONFIG_CMD_LED /* LED support */
151 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
152 #define CONFIG_CMD_NFS /* NFS support */
153 #define CONFIG_CMD_PING
154 #define CONFIG_CMD_DHCP
155 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */
156 #define CONFIG_CMD_GPIO /* Enable gpio command */
158 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
159 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
160 #undef CONFIG_CMD_IMI /* iminfo */
161 #undef CONFIG_CMD_IMLS /* List all found images */
163 #define CONFIG_SYS_NO_FLASH
164 #define CONFIG_SYS_I2C
165 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
166 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
167 #define CONFIG_SYS_I2C_OMAP34XX
168 #define CONFIG_VIDEO_OMAP3 /* DSS Support */
173 #define CONFIG_TWL4030_POWER 1
174 #define CONFIG_TWL4030_LED 1
179 #define CONFIG_SYS_NAND_QUIET_TEST 1
180 #define CONFIG_NAND_OMAP_GPMC
181 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
183 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
184 /* to access nand at */
186 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
188 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
191 /* Environment information */
192 #define CONFIG_BOOTDELAY 3
194 #define CONFIG_EXTRA_ENV_SETTINGS \
195 "loadaddr=0x80200000\0" \
196 "rdaddr=0x81000000\0" \
197 "fdt_high=0xffffffff\0" \
198 "fdtaddr=0x80f80000\0" \
200 "bootfile=uImage\0" \
201 "ramdisk=ramdisk.gz\0" \
204 "console=ttyO2,115200n8\0" \
210 "dvimode=640x480MR-16@60\0" \
211 "defaultdisplay=dvi\0" \
213 "mmcroot=/dev/mmcblk0p2 rw\0" \
214 "mmcrootfstype=ext3 rootwait\0" \
215 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
216 "nandrootfstype=ubifs\0" \
217 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
218 "ramrootfstype=ext2\0" \
219 "mmcargs=setenv bootargs console=${console} " \
221 "mpurate=${mpurate} " \
225 "omapfb.mode=dvi:${dvimode} " \
226 "omapdss.def_disp=${defaultdisplay} " \
228 "rootfstype=${mmcrootfstype}\0" \
229 "nandargs=setenv bootargs console=${console} " \
231 "mpurate=${mpurate} " \
235 "omapfb.mode=dvi:${dvimode} " \
236 "omapdss.def_disp=${defaultdisplay} " \
237 "root=${nandroot} " \
238 "rootfstype=${nandrootfstype}\0" \
240 "if test $beaglerev = AxBx; then " \
241 "setenv fdtfile omap3-beagle.dtb; fi; " \
242 "if test $beaglerev = Cx; then " \
243 "setenv fdtfile omap3-beagle.dtb; fi; " \
244 "if test $beaglerev = C4; then " \
245 "setenv fdtfile omap3-beagle.dtb; fi; " \
246 "if test $beaglerev = xMAB; then " \
247 "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
248 "if test $beaglerev = xMC; then " \
249 "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
250 "if test $fdtfile = undefined; then " \
251 "echo WARNING: Could not determine device tree to use; fi; \0" \
252 "bootenv=uEnv.txt\0" \
253 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
254 "importbootenv=echo Importing environment from mmc ...; " \
255 "env import -t $loadaddr $filesize\0" \
256 "ramargs=setenv bootargs console=${console} " \
258 "mpurate=${mpurate} " \
261 "omapfb.mode=dvi:${dvimode} " \
262 "omapdss.def_disp=${defaultdisplay} " \
264 "rootfstype=${ramrootfstype}\0" \
265 "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
266 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
267 "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
268 "mmcboot=echo Booting from mmc ...; " \
270 "bootm ${loadaddr}\0" \
271 "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
273 "bootz ${loadaddr} - ${fdtaddr}\0" \
274 "nandboot=echo Booting from nand ...; " \
276 "nand read ${loadaddr} 280000 400000; " \
277 "bootm ${loadaddr}\0" \
278 "ramboot=echo Booting from ramdisk ...; " \
280 "bootm ${loadaddr}\0" \
281 "userbutton=if gpio input 173; then run userbutton_xm; " \
282 "else run userbutton_nonxm; fi;\0" \
283 "userbutton_xm=gpio input 4;\0" \
284 "userbutton_nonxm=gpio input 7;\0"
285 /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
286 #define CONFIG_BOOTCOMMAND \
288 "mmc dev ${mmcdev}; if mmc rescan; then " \
289 "if run userbutton; then " \
290 "setenv bootenv uEnv.txt;" \
292 "setenv bootenv user.txt;" \
294 "echo SD/MMC found on device ${mmcdev};" \
295 "if run loadbootenv; then " \
296 "echo Loaded environment from ${bootenv};" \
297 "run importbootenv;" \
299 "if test -n $uenvcmd; then " \
300 "echo Running uenvcmd ...;" \
303 "if run loadimage; then " \
308 "setenv bootfile zImage;" \
309 "if run loadimage; then " \
314 #define CONFIG_AUTO_COMPLETE 1
316 * Miscellaneous configurable options
318 #define CONFIG_SYS_LONGHELP /* undef to save memory */
319 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
320 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
321 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
322 /* Print Buffer Size */
323 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
324 sizeof(CONFIG_SYS_PROMPT) + 16)
325 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
326 /* Boot Argument Buffer Size */
327 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
329 #define CONFIG_SYS_ALT_MEMTEST 1
330 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
332 #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
333 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
335 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
339 * OMAP3 has 12 GP timers, they can be driven by the system clock
340 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
341 * This rate is divided by a local divisor.
343 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
344 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
346 /*-----------------------------------------------------------------------
347 * Physical Memory Map
349 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
350 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
351 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
353 /*-----------------------------------------------------------------------
354 * FLASH and environment organization
357 /* **** PISMO SUPPORT *** */
359 /* Configure the PISMO */
360 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
361 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
363 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
365 #if defined(CONFIG_CMD_NAND)
366 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
369 /* Monitor at start of flash */
370 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
371 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
373 #define CONFIG_ENV_IS_IN_NAND 1
374 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
375 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
377 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
378 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
379 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
381 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
382 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
383 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
384 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
385 CONFIG_SYS_INIT_RAM_SIZE - \
386 GENERATED_GBL_DATA_SIZE)
388 #define CONFIG_OMAP3_SPI
390 #define CONFIG_SYS_CACHELINE_SIZE 64
392 /* Defines for SPL */
394 #define CONFIG_SPL_FRAMEWORK
395 #define CONFIG_SPL_NAND_SIMPLE
396 #define CONFIG_SPL_TEXT_BASE 0x40200800
397 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
398 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
400 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
401 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
403 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
404 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
405 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
406 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
408 #define CONFIG_SPL_BOARD_INIT
409 #define CONFIG_SPL_LIBCOMMON_SUPPORT
410 #define CONFIG_SPL_LIBDISK_SUPPORT
411 #define CONFIG_SPL_I2C_SUPPORT
412 #define CONFIG_SPL_LIBGENERIC_SUPPORT
413 #define CONFIG_SPL_MMC_SUPPORT
414 #define CONFIG_SPL_FAT_SUPPORT
415 #define CONFIG_SPL_SERIAL_SUPPORT
416 #define CONFIG_SPL_NAND_SUPPORT
417 #define CONFIG_SPL_NAND_BASE
418 #define CONFIG_SPL_NAND_DRIVERS
419 #define CONFIG_SPL_NAND_ECC
420 #define CONFIG_SPL_GPIO_SUPPORT
421 #define CONFIG_SPL_POWER_SUPPORT
422 #define CONFIG_SPL_OMAP3_ID_NAND
423 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
425 /* NAND boot config */
426 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
427 #define CONFIG_SYS_NAND_PAGE_COUNT 64
428 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
429 #define CONFIG_SYS_NAND_OOBSIZE 64
430 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
431 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
432 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
434 #define CONFIG_SYS_NAND_ECCSIZE 512
435 #define CONFIG_SYS_NAND_ECCBYTES 3
436 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
437 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
438 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
441 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
442 * 64 bytes before this address should be set aside for u-boot.img's
443 * header. That is 0x800FFFC0--0x80100000 should not be used for any
446 #define CONFIG_SYS_TEXT_BASE 0x80100000
447 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
448 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
450 #endif /* __CONFIG_H */