2 * Configuration settings for the QUIPOS Cairo board.
4 * Copyright (C) DENX GmbH
7 * Albert ARIBAUD <albert.aribaud@3adev.fr>
9 * Derived from EVM code by
10 * Manikandan Pillai <mani.pillai@ti.com>
11 * Itself derived from Beagle Board and 3430 SDP code by
12 * Richard Woodruff <r-woodruff2@ti.com>
13 * Syed Mohammed Khasim <khasim@ti.com>
15 * Also derived from include/configs/omap3_beagle.h
17 * SPDX-License-Identifier: GPL-2.0+
20 #ifndef __OMAP3_CAIRO_CONFIG_H
21 #define __OMAP3_CAIRO_CONFIG_H
23 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
27 * 64 bytes before this address should be set aside for u-boot.img's
28 * header. That is 0x800FFFC0--0x80100000 should not be used for any
29 * other needs. We use this rather than the inherited defines from
30 * ti_armv7_common.h for backwards compatibility.
32 #define CONFIG_SYS_TEXT_BASE 0x80100000
33 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
35 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
36 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
37 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
39 #include <configs/ti_omap3_common.h>
41 #define CONFIG_MISC_INIT_R
43 #define CONFIG_REVISION_TAG 1
44 #define CONFIG_ENV_OVERWRITE
46 /* Enable Multi Bus support for I2C */
47 #define CONFIG_I2C_MULTI_BUS 1
49 /* Probe all devices */
50 #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
55 #define CONFIG_TWL4030_LED 1
60 #define CONFIG_NAND_OMAP_GPMC
61 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
63 #define CONFIG_EXTRA_ENV_SETTINGS \
65 "fdt_high=0x87000000\0" \
67 "fec_addr=00:50:C2:7E:90:F0\0" \
68 "netmask=255.255.255.0\0" \
69 "ipaddr=192.168.2.9\0" \
70 "gateway=192.168.2.1\0" \
71 "serverip=192.168.2.10\0" \
72 "nfshost=192.168.2.10\0" \
76 "bootargs_mmc_ramdisk=mem=128M " \
77 "console=ttyO1,115200n8 " \
78 "root=/dev/ram0 rw " \
79 "initrd=0x81600000,16M " \
80 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
81 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
82 "mmcboot=mmc init; " \
83 "fatload mmc 0 0x80000000 uImage; " \
84 "fatload mmc 0 0x81600000 ramdisk.gz; " \
85 "setenv bootargs ${bootargs_mmc_ramdisk}; " \
86 "bootm 0x80000000\0" \
87 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
89 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
90 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
91 "omap_vout.vid1_static_vrfb_alloc=y\0" \
92 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
93 "bootm 0x80000000\0" \
94 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
95 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
96 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
97 "omapfb.rotate_type=1\0" \
98 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
99 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
100 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
101 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
102 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
103 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
104 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
105 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
106 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
107 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
108 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
109 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
110 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
111 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
112 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
113 "nand erase 0 20000; " \
114 "fatload mmc 0 0x81600000 MLO; " \
116 "nand write.i 0x81600000 0 20000;\0" \
117 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
118 "nand erase 80000 40000; " \
119 "fatload mmc 0 0x81600000 u-boot.bin; " \
121 "nand write.i 0x81600000 80000 40000;\0" \
122 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
123 "nand erase 280000 300000; " \
124 "fatload mmc 0 0x81600000 uImage; " \
126 "nand write.i 0x81600000 280000 300000;\0" \
127 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
129 "nand write.jffs2 0x680000 0xFF ${filesize}; " \
130 "nand erase 680000 ${filesize}; " \
131 "nand write.jffs2 81600000 680000 ${filesize};\0" \
132 "flash_scrub=nand scrub; " \
133 "run flash_xloader; " \
134 "run flash_uboot; " \
135 "run flash_kernel; " \
136 "run flash_rootfs;\0" \
137 "flash_all=run ledred; " \
138 "nand erase.chip; " \
140 "run flash_xloader; " \
141 "run flash_uboot; " \
142 "run flash_kernel; " \
143 "run flash_rootfs; " \
145 "run boot_nand; \0" \
147 #define CONFIG_BOOTCOMMAND \
148 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
149 "else run boot_nand; fi"
152 * OMAP3 has 12 GP timers, they can be driven by the system clock
153 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
154 * This rate is divided by a local divisor.
156 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
158 /*-----------------------------------------------------------------------
159 * FLASH and environment organization
162 /* **** PISMO SUPPORT *** */
163 #if defined(CONFIG_CMD_NAND)
164 #define CONFIG_SYS_FLASH_BASE NAND_BASE
167 /* Monitor at start of flash */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
169 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
171 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
172 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
173 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
175 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
176 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
177 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
179 /* Defines for SPL */
180 #define CONFIG_SPL_OMAP3_ID_NAND
182 /* NAND boot config */
183 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
184 #define CONFIG_SYS_NAND_PAGE_COUNT 64
185 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
186 #define CONFIG_SYS_NAND_OOBSIZE 64
187 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
188 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
189 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
191 #define CONFIG_SYS_NAND_ECCSIZE 512
192 #define CONFIG_SYS_NAND_ECCBYTES 3
193 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
194 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
195 /* NAND: SPL falcon mode configs */
196 #ifdef CONFIG_SPL_OS_BOOT
197 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
201 #define CONFIG_BOOTFILE "uImage"
203 /* Override OMAP3 common serial console configuration from UART3
206 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
207 * are needed and peripheral clocks for UART2 must be enabled in
208 * function per_clocks_enable().
210 #undef CONFIG_CONS_INDEX
211 #define CONFIG_CONS_INDEX 2
212 #ifdef CONFIG_SPL_BUILD
213 #undef CONFIG_SYS_NS16550_COM3
214 #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
215 #undef CONFIG_SERIAL3
216 #define CONFIG_SERIAL2
219 /* Provide the MACH_TYPE value the vendor kernel requires */
220 #define CONFIG_MACH_TYPE 3063
222 /*-----------------------------------------------------------------------
223 * FLASH and environment organization
226 /* **** PISMO SUPPORT *** */
228 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
230 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
232 /*-----------------------------------------------------------------------
233 * CFI FLASH driver setup
235 /* timeout values are in ticks */
236 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
237 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
239 /* Flash banks JFFS2 should use */
240 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
241 CONFIG_SYS_MAX_NAND_DEVICE)
242 #define CONFIG_SYS_JFFS2_MEM_NAND
243 /* use flash_info[2] */
244 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
245 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
247 #endif /* __OMAP3_CAIRO_CONFIG_H */