2 * Configuration settings for the Gumstix Overo board.
4 * SPDX-License-Identifier: GPL-2.0+
11 * High Level Configuration Options
13 #define CONFIG_OMAP /* in a TI OMAP core */
14 #define CONFIG_OMAP34XX /* which is a 34XX */
15 #define CONFIG_OMAP3_OVERO /* working with overo */
16 #define CONFIG_OMAP_GPIO
17 #define CONFIG_OMAP_COMMON
19 #define CONFIG_SDRC /* The chip has SDRC controller */
21 #include <asm/arch/cpu.h> /* get chip and board defs */
22 #include <asm/arch/omap3.h>
25 * Display CPU and Board information
27 #define CONFIG_DISPLAY_CPUINFO
28 #define CONFIG_DISPLAY_BOARDINFO
31 #define V_OSCK 26000000 /* Clock output from T2 */
32 #define V_SCLK (V_OSCK >> 1)
34 #define CONFIG_MISC_INIT_R
36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG
39 #define CONFIG_REVISION_TAG
41 #define CONFIG_OF_LIBFDT
44 * Size of malloc() pool
46 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
48 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
55 * NS16550 Configuration
57 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
59 #define CONFIG_SYS_NS16550
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
65 * select serial console configuration
67 #define CONFIG_CONS_INDEX 3
68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
69 #define CONFIG_SERIAL3 3
71 /* allow to overwrite serial and ethaddr */
72 #define CONFIG_ENV_OVERWRITE
73 #define CONFIG_BAUDRATE 115200
74 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
76 #define CONFIG_GENERIC_MMC
78 #define CONFIG_OMAP_HSMMC
79 #define CONFIG_DOS_PARTITION
81 /* commands to include */
82 #include <config_cmd_default.h>
84 #define CONFIG_CMD_CACHE
85 #define CONFIG_CMD_EXT2 /* EXT2 Support */
86 #define CONFIG_CMD_FAT /* FAT support */
87 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
89 #define CONFIG_CMD_I2C /* I2C serial bus support */
90 #define CONFIG_CMD_MMC /* MMC support */
91 #define CONFIG_CMD_NAND /* NAND support */
93 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
94 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
95 #undef CONFIG_CMD_IMI /* iminfo */
96 #undef CONFIG_CMD_IMLS /* List all found images */
97 #undef CONFIG_CMD_NFS /* NFS support */
98 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
100 #define CONFIG_SYS_NO_FLASH
101 #define CONFIG_SYS_I2C
102 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
103 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
104 #define CONFIG_SYS_I2C_OMAP34XX
109 #define CONFIG_TWL4030_POWER
110 #define CONFIG_TWL4030_LED
115 #define CONFIG_SYS_NAND_QUIET_TEST
116 #define CONFIG_NAND_OMAP_GPMC
117 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
119 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
122 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
124 #define CONFIG_JFFS2_NAND
125 /* nand device jffs2 lives on */
126 #define CONFIG_JFFS2_DEV "nand0"
127 /* start of jffs2 partition */
128 #define CONFIG_JFFS2_PART_OFFSET 0x680000
129 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
132 /* Environment information */
133 #define CONFIG_BOOTDELAY 5
135 #define CONFIG_EXTRA_ENV_SETTINGS \
136 "loadaddr=0x82000000\0" \
137 "console=ttyO2,115200n8\0" \
141 "dvimode=1024x768MR-16@60\0" \
142 "defaultdisplay=dvi\0" \
144 "mmcroot=/dev/mmcblk0p2 rw\0" \
145 "mmcrootfstype=ext3 rootwait\0" \
146 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
147 "nandrootfstype=ubifs\0" \
148 "mmcargs=setenv bootargs console=${console} " \
150 "mpurate=${mpurate} " \
152 "omapfb.mode=dvi:${dvimode} " \
153 "omapdss.def_disp=${defaultdisplay} " \
155 "rootfstype=${mmcrootfstype}\0" \
156 "nandargs=setenv bootargs console=${console} " \
158 "mpurate=${mpurate} " \
160 "omapfb.mode=dvi:${dvimode} " \
161 "omapdss.def_disp=${defaultdisplay} " \
162 "root=${nandroot} " \
163 "rootfstype=${nandrootfstype}\0" \
164 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
165 "bootscript=echo Running bootscript from mmc ...; " \
166 "source ${loadaddr}\0" \
167 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
168 "mmcboot=echo Booting from mmc ...; " \
170 "bootm ${loadaddr}\0" \
171 "nandboot=echo Booting from nand ...; " \
173 "nand read ${loadaddr} 280000 400000; " \
174 "bootm ${loadaddr}\0" \
176 #define CONFIG_BOOTCOMMAND \
177 "mmc dev ${mmcdev}; if mmc rescan; then " \
178 "if run loadbootscript; then " \
181 "if run loaduimage; then " \
183 "else run nandboot; " \
186 "else run nandboot; fi"
188 #define CONFIG_AUTO_COMPLETE 1
190 * Miscellaneous configurable options
192 #define CONFIG_SYS_LONGHELP /* undef to save memory */
193 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
194 #define CONFIG_SYS_PROMPT "Overo # "
195 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
196 /* Print Buffer Size */
197 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
198 sizeof(CONFIG_SYS_PROMPT) + 16)
199 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
201 /* Boot Argument Buffer Size */
202 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
203 /* memtest works on */
204 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
205 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
206 0x01F00000) /* 31MB */
208 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
211 * OMAP3 has 12 GP timers, they can be driven by the system clock
212 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
213 * This rate is divided by a local divisor.
215 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
216 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
218 /*-----------------------------------------------------------------------
219 * Physical Memory Map
221 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
222 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
223 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
225 /*-----------------------------------------------------------------------
226 * FLASH and environment organization
229 /* **** PISMO SUPPORT *** */
231 /* Configure the PISMO */
232 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
233 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
235 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
237 #if defined(CONFIG_CMD_NAND)
238 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
241 /* Monitor at start of flash */
242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
243 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
245 #define CONFIG_ENV_IS_IN_NAND
246 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
247 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
249 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
250 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
251 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
253 #if defined(CONFIG_CMD_NET)
254 /*----------------------------------------------------------------------------
255 * SMSC9211 Ethernet from SMSC9118 family
256 *----------------------------------------------------------------------------
259 #define CONFIG_SMC911X
260 #define CONFIG_SMC911X_32_BIT
261 #define CONFIG_SMC911X_BASE 0x2C000000
263 #endif /* (CONFIG_CMD_NET) */
266 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
267 * and older u-boot.bin with the new U-Boot SPL.
269 #define CONFIG_SYS_TEXT_BASE 0x80008000
270 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
271 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
272 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
273 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
274 CONFIG_SYS_INIT_RAM_SIZE - \
275 GENERATED_GBL_DATA_SIZE)
277 #define CONFIG_SYS_CACHELINE_SIZE 64
279 /* Defines for SPL */
281 #define CONFIG_SPL_FRAMEWORK
282 #define CONFIG_SPL_NAND_SIMPLE
283 #define CONFIG_SPL_TEXT_BASE 0x40200800
284 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
285 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
287 /* move malloc and bss high to prevent clashing with the main image */
288 #define CONFIG_SYS_SPL_MALLOC_START 0x87000000
289 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
290 #define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
291 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
293 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
294 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
295 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
296 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
298 #define CONFIG_SPL_BOARD_INIT
299 #define CONFIG_SPL_LIBCOMMON_SUPPORT
300 #define CONFIG_SPL_LIBDISK_SUPPORT
301 #define CONFIG_SPL_I2C_SUPPORT
302 #define CONFIG_SPL_LIBGENERIC_SUPPORT
303 #define CONFIG_SPL_MMC_SUPPORT
304 #define CONFIG_SPL_FAT_SUPPORT
305 #define CONFIG_SPL_SERIAL_SUPPORT
306 #define CONFIG_SPL_NAND_SUPPORT
307 #define CONFIG_SPL_NAND_BASE
308 #define CONFIG_SPL_NAND_DRIVERS
309 #define CONFIG_SPL_NAND_ECC
310 #define CONFIG_SPL_GPIO_SUPPORT
311 #define CONFIG_SPL_POWER_SUPPORT
312 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
314 /* NAND boot config */
315 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
316 #define CONFIG_SYS_NAND_PAGE_COUNT 64
317 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
318 #define CONFIG_SYS_NAND_OOBSIZE 64
319 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
320 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
321 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
323 #define CONFIG_SYS_NAND_ECCSIZE 512
324 #define CONFIG_SYS_NAND_ECCBYTES 3
325 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
326 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
327 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
329 #endif /* __CONFIG_H */