2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
10 * SPDX-License-Identifier: GPL-2.0+
17 * High Level Configuration Options
19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
21 #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
22 #define CONFIG_OMAP_COMMON
24 #define CONFIG_SDRC /* The chip has SDRC controller */
26 #include <asm/arch/cpu.h> /* get chip and board defs */
27 #include <asm/arch/omap3.h>
30 * Display CPU and Board information
32 #define CONFIG_DISPLAY_CPUINFO 1
33 #define CONFIG_DISPLAY_BOARDINFO 1
36 #define V_OSCK 26000000 /* Clock output from T2 */
37 #define V_SCLK (V_OSCK >> 1)
39 #define CONFIG_MISC_INIT_R
41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS 1
43 #define CONFIG_INITRD_TAG 1
44 #define CONFIG_REVISION_TAG 1
46 #define CONFIG_OF_LIBFDT 1
49 * Size of malloc() pool
51 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
60 * NS16550 Configuration
62 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
64 #define CONFIG_SYS_NS16550
65 #define CONFIG_SYS_NS16550_SERIAL
66 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
67 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
70 * select serial console configuration
72 #define CONFIG_CONS_INDEX 3
73 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
74 #define CONFIG_SERIAL3 3 /* UART3 */
76 /* allow to overwrite serial and ethaddr */
77 #define CONFIG_ENV_OVERWRITE
78 #define CONFIG_BAUDRATE 115200
79 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
81 #define CONFIG_GENERIC_MMC 1
83 #define CONFIG_OMAP_HSMMC 1
84 #define CONFIG_DOS_PARTITION 1
87 #define CONFIG_MUSB_UDC 1
88 #define CONFIG_USB_OMAP3 1
89 #define CONFIG_TWL4030_USB 1
91 /* USB device configuration */
92 #define CONFIG_USB_DEVICE 1
93 #define CONFIG_USB_TTY 1
94 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
95 /* Change these to suit your needs */
96 #define CONFIG_USBD_VENDORID 0x0451
97 #define CONFIG_USBD_PRODUCTID 0x5678
98 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
99 #define CONFIG_USBD_PRODUCT_NAME "Zoom1"
101 /* commands to include */
102 #include <config_cmd_default.h>
104 #define CONFIG_CMD_EXT2 /* EXT2 Support */
105 #define CONFIG_CMD_FAT /* FAT support */
106 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
108 #define CONFIG_CMD_I2C /* I2C serial bus support */
109 #define CONFIG_CMD_MMC /* MMC support */
110 #define CONFIG_CMD_NAND /* NAND support */
111 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
113 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
114 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
115 #undef CONFIG_CMD_IMI /* iminfo */
116 #undef CONFIG_CMD_IMLS /* List all found images */
117 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
118 #undef CONFIG_CMD_NFS /* NFS support */
120 #define CONFIG_SYS_NO_FLASH
121 #define CONFIG_SYS_I2C
122 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
123 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
124 #define CONFIG_SYS_I2C_OMAP34XX
129 #define CONFIG_TWL4030_POWER 1
130 #define CONFIG_TWL4030_LED 1
135 #define CONFIG_NAND_OMAP_GPMC
136 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
138 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
139 /* to access nand at */
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
143 #define CONFIG_JFFS2_NAND
144 /* nand device jffs2 lives on */
145 #define CONFIG_JFFS2_DEV "nand0"
146 /* start of jffs2 partition */
147 #define CONFIG_JFFS2_PART_OFFSET 0x680000
148 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
151 /* Environment information */
152 #define CONFIG_BOOTDELAY 10
154 #define CONFIG_EXTRA_ENV_SETTINGS \
155 "loadaddr=0x82000000\0" \
157 "console=ttyS2,115200n8\0" \
159 "videomode=1024x768@60,vxres=1024,vyres=768\0" \
160 "videospec=omapfb:vram:2M,vram:4M\0" \
161 "mmcargs=setenv bootargs console=${console} " \
162 "video=${videospec},mode:${videomode} " \
163 "root=/dev/mmcblk0p2 rw " \
164 "rootfstype=ext3 rootwait\0" \
165 "nandargs=setenv bootargs console=${console} " \
166 "video=${videospec},mode:${videomode} " \
167 "root=/dev/mtdblock4 rw " \
168 "rootfstype=jffs2\0" \
169 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
170 "bootscript=echo Running bootscript from mmc ...; " \
171 "source ${loadaddr}\0" \
172 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
173 "mmcboot=echo Booting from mmc ...; " \
175 "bootm ${loadaddr}\0" \
176 "nandboot=echo Booting from nand ...; " \
178 "nand read ${loadaddr} 280000 400000; " \
179 "bootm ${loadaddr}\0" \
181 #define CONFIG_BOOTCOMMAND \
182 "mmc dev ${mmcdev}; if mmc rescan; then " \
183 "if run loadbootscript; then " \
186 "if run loaduimage; then " \
188 "else run nandboot; " \
191 "else run nandboot; fi"
193 #define CONFIG_AUTO_COMPLETE 1
195 * Miscellaneous configurable options
197 #define CONFIG_SYS_LONGHELP /* undef to save memory */
198 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
199 #define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
200 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
201 /* Print Buffer Size */
202 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
203 sizeof(CONFIG_SYS_PROMPT) + 16)
204 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
205 /* Boot Argument Buffer Size */
206 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
208 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
210 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
211 0x01F00000) /* 31MB */
213 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
216 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
217 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
218 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
219 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
220 CONFIG_SYS_INIT_RAM_SIZE - \
221 GENERATED_GBL_DATA_SIZE)
223 * OMAP3 has 12 GP timers, they can be driven by the system clock
224 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
225 * This rate is divided by a local divisor.
227 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
228 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
230 /*-----------------------------------------------------------------------
231 * Physical Memory Map
233 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
234 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
235 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
237 /*-----------------------------------------------------------------------
238 * FLASH and environment organization
241 /* **** PISMO SUPPORT *** */
243 /* Configure the PISMO */
244 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
245 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
247 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
249 #if defined(CONFIG_CMD_NAND)
250 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
253 /* Monitor at start of flash */
254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
255 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
257 #define CONFIG_ENV_IS_IN_NAND 1
258 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
259 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
261 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
262 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
263 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
265 #define CONFIG_SYS_CACHELINE_SIZE 64
267 #endif /* __CONFIG_H */