2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * High Level Configuration Options
35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
36 #define CONFIG_OMAP 1 /* in a TI OMAP core */
37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
39 #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
41 #include <asm/arch/cpu.h> /* get chip and board defs */
42 #include <asm/arch/omap3.h>
45 * Display CPU and Board information
47 #define CONFIG_DISPLAY_CPUINFO 1
48 #define CONFIG_DISPLAY_BOARDINFO 1
51 #define V_OSCK 26000000 /* Clock output from T2 */
52 #define V_SCLK (V_OSCK >> 1)
54 #undef CONFIG_USE_IRQ /* no support for IRQs */
55 #define CONFIG_MISC_INIT_R
57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58 #define CONFIG_SETUP_MEMORY_TAGS 1
59 #define CONFIG_INITRD_TAG 1
60 #define CONFIG_REVISION_TAG 1
63 * Size of malloc() pool
65 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
68 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
76 * NS16550 Configuration
78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80 #define CONFIG_SYS_NS16550
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86 * select serial console configuration
88 #define CONFIG_CONS_INDEX 3
89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90 #define CONFIG_SERIAL3 3 /* UART3 */
92 /* allow to overwrite serial and ethaddr */
93 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
98 #define CONFIG_OMAP3_MMC 1
99 #define CONFIG_DOS_PARTITION 1
101 /* DDR - I use Micron DDR */
102 #define CONFIG_OMAP3_MICRON_DDR 1
105 #define CONFIG_MUSB_UDC 1
106 #define CONFIG_USB_OMAP3 1
107 #define CONFIG_TWL4030_USB 1
109 /* USB device configuration */
110 #define CONFIG_USB_DEVICE 1
111 #define CONFIG_USB_TTY 1
112 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
113 /* Change these to suit your needs */
114 #define CONFIG_USBD_VENDORID 0x0451
115 #define CONFIG_USBD_PRODUCTID 0x5678
116 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
117 #define CONFIG_USBD_PRODUCT_NAME "Zoom1"
119 /* commands to include */
120 #include <config_cmd_default.h>
122 #define CONFIG_CMD_EXT2 /* EXT2 Support */
123 #define CONFIG_CMD_FAT /* FAT support */
124 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
126 #define CONFIG_CMD_I2C /* I2C serial bus support */
127 #define CONFIG_CMD_MMC /* MMC support */
128 #define CONFIG_CMD_NAND /* NAND support */
129 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
131 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
132 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
133 #undef CONFIG_CMD_IMI /* iminfo */
134 #undef CONFIG_CMD_IMLS /* List all found images */
135 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
136 #undef CONFIG_CMD_NFS /* NFS support */
138 #define CONFIG_SYS_NO_FLASH
139 #define CONFIG_HARD_I2C 1
140 #define CONFIG_SYS_I2C_SPEED 100000
141 #define CONFIG_SYS_I2C_SLAVE 1
142 #define CONFIG_SYS_I2C_BUS 0
143 #define CONFIG_SYS_I2C_BUS_SELECT 1
144 #define CONFIG_DRIVER_OMAP34XX_I2C 1
149 #define CONFIG_TWL4030_POWER 1
150 #define CONFIG_TWL4030_LED 1
155 #define CONFIG_NAND_OMAP_GPMC
156 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
158 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
159 /* to access nand at */
161 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
165 #define CONFIG_JFFS2_NAND
166 /* nand device jffs2 lives on */
167 #define CONFIG_JFFS2_DEV "nand0"
168 /* start of jffs2 partition */
169 #define CONFIG_JFFS2_PART_OFFSET 0x680000
170 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
173 /* Environment information */
174 #define CONFIG_BOOTDELAY 10
176 #define CONFIG_EXTRA_ENV_SETTINGS \
177 "loadaddr=0x82000000\0" \
179 "console=ttyS2,115200n8\0" \
180 "videomode=1024x768@60,vxres=1024,vyres=768\0" \
181 "videospec=omapfb:vram:2M,vram:4M\0" \
182 "mmcargs=setenv bootargs console=${console} " \
183 "video=${videospec},mode:${videomode} " \
184 "root=/dev/mmcblk0p2 rw " \
185 "rootfstype=ext3 rootwait\0" \
186 "nandargs=setenv bootargs console=${console} " \
187 "video=${videospec},mode:${videomode} " \
188 "root=/dev/mtdblock4 rw " \
189 "rootfstype=jffs2\0" \
190 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
191 "bootscript=echo Running bootscript from mmc ...; " \
192 "source ${loadaddr}\0" \
193 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
194 "mmcboot=echo Booting from mmc ...; " \
196 "bootm ${loadaddr}\0" \
197 "nandboot=echo Booting from nand ...; " \
199 "nand read ${loadaddr} 280000 400000; " \
200 "bootm ${loadaddr}\0" \
202 #define CONFIG_BOOTCOMMAND \
203 "if mmc init; then " \
204 "if run loadbootscript; then " \
207 "if run loaduimage; then " \
209 "else run nandboot; " \
212 "else run nandboot; fi"
214 #define CONFIG_AUTO_COMPLETE 1
216 * Miscellaneous configurable options
218 #define V_PROMPT "OMAP3 Zoom1# "
220 #define CONFIG_SYS_LONGHELP /* undef to save memory */
221 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
222 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
223 #define CONFIG_SYS_PROMPT V_PROMPT
224 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
225 /* Print Buffer Size */
226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
227 sizeof(CONFIG_SYS_PROMPT) + 16)
228 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
229 /* Boot Argument Buffer Size */
230 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
232 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
234 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
235 0x01F00000) /* 31MB */
237 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
241 * OMAP3 has 12 GP timers, they can be driven by the system clock
242 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
243 * This rate is divided by a local divisor.
245 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
246 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
247 #define CONFIG_SYS_HZ 1000
249 /*-----------------------------------------------------------------------
252 * The stack sizes are set up in start.S using the settings below
254 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
255 #ifdef CONFIG_USE_IRQ
256 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
257 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
260 /*-----------------------------------------------------------------------
261 * Physical Memory Map
263 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
264 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
265 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
266 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
268 /* SDRAM Bank Allocation method */
271 /*-----------------------------------------------------------------------
272 * FLASH and environment organization
275 /* **** PISMO SUPPORT *** */
277 /* Configure the PISMO */
278 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
279 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
281 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
283 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
284 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
286 #define CONFIG_SYS_FLASH_BASE boot_flash_base
288 /* Monitor at start of flash */
289 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
290 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
292 #define CONFIG_ENV_IS_IN_NAND 1
293 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
294 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
296 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
297 #define CONFIG_ENV_OFFSET boot_flash_off
298 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
300 /*-----------------------------------------------------------------------
301 * CFI FLASH driver setup
303 /* timeout values are in ticks */
304 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
305 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
307 /* Flash banks JFFS2 should use */
308 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
309 CONFIG_SYS_MAX_NAND_DEVICE)
310 #define CONFIG_SYS_JFFS2_MEM_NAND
311 /* use flash_info[2] */
312 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
313 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
316 extern struct gpmc *gpmc_cfg;
317 extern unsigned int boot_flash_base;
318 extern volatile unsigned int boot_flash_env_addr;
319 extern unsigned int boot_flash_off;
320 extern unsigned int boot_flash_sec;
321 extern unsigned int boot_flash_type;
324 #endif /* __CONFIG_H */