git.sur5r.net Git - u-boot/blob - include/configs/omap3_zoom1.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  * Nishanth Menon <nm@ti.com>
   7  *
   8  * Configuration settings for the TI OMAP3430 Zoom MDK board.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31 #include <asm/sizes.h>
  32
  33 /*
  34  * High Level Configuration Options
  35  */
  36 #define CONFIG_ARMCORTEXA8      1       /* This is an ARM V7 CPU core */
  37 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  38 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  39 #define CONFIG_OMAP3430         1       /* which is in a 3430 */
  40 #define CONFIG_OMAP3_ZOOM1      1       /* working with Zoom MDK Rev1 */
  41
  42 #include <asm/arch/cpu.h>               /* get chip and board defs */
  43 #include <asm/arch/omap3.h>
  44
  45 /* Clock Defines */
  46 #define V_OSCK                  26000000        /* Clock output from T2 */
  47 #define V_SCLK                  (V_OSCK >> 1)
  48
  49 #undef CONFIG_USE_IRQ                           /* no support for IRQs */
  50 #define CONFIG_MISC_INIT_R
  51
  52 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  53 #define CONFIG_SETUP_MEMORY_TAGS        1
  54 #define CONFIG_INITRD_TAG               1
  55 #define CONFIG_REVISION_TAG             1
  56
  57 /*
  58  * Size of malloc() pool
  59  */
  60 #define CONFIG_ENV_SIZE                 SZ_128K /* Total Size Environment */
  61                                                 /* Sector */
  62 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
  63 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* bytes reserved for */
  64                                                 /* initial data */
  65
  66 /*
  67  * Hardware drivers
  68  */
  69
  70 /*
  71  * NS16550 Configuration
  72  */
  73 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  74
  75 #define CONFIG_SYS_NS16550
  76 #define CONFIG_SYS_NS16550_SERIAL
  77 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  78 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  79
  80 /*
  81  * select serial console configuration
  82  */
  83 #define CONFIG_CONS_INDEX               3
  84 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  85 #define CONFIG_SERIAL3                  3       /* UART3 */
  86
  87 /* allow to overwrite serial and ethaddr */
  88 #define CONFIG_ENV_OVERWRITE
  89 #define CONFIG_BAUDRATE                 115200
  90 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  91                                         115200}
  92 #define CONFIG_MMC                      1
  93 #define CONFIG_OMAP3_MMC                1
  94 #define CONFIG_DOS_PARTITION            1
  95
  96 /* commands to include */
  97 #include <config_cmd_default.h>
  98
  99 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 100 #define CONFIG_CMD_FAT          /* FAT support                  */
 101 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 102
 103 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 104 #define CONFIG_CMD_MMC          /* MMC support                  */
 105 #define CONFIG_CMD_NAND         /* NAND support                 */
 106
 107 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 108 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 109 #undef CONFIG_CMD_IMI           /* iminfo                       */
 110 #undef CONFIG_CMD_IMLS          /* List all found images        */
 111 #undef CONFIG_CMD_NET           /* bootp, tftpboot, rarpboot    */
 112 #undef CONFIG_CMD_NFS           /* NFS support                  */
 113
 114 #define CONFIG_SYS_NO_FLASH
 115 #define CONFIG_SYS_I2C_SPEED            100000
 116 #define CONFIG_SYS_I2C_SLAVE            1
 117 #define CONFIG_SYS_I2C_BUS              0
 118 #define CONFIG_SYS_I2C_BUS_SELECT       1
 119 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 120
 121 /*
 122  * Board NAND Info.
 123  */
 124 #define CONFIG_NAND_OMAP_GPMC
 125 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 126                                                         /* to access nand */
 127 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 128                                                         /* to access nand at */
 129                                                         /* CS0 */
 130 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 131
 132 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 133                                                         /* devices */
 134 #define SECTORSIZE                      512
 135
 136 #define NAND_ALLOW_ERASE_ALL
 137 #define ADDR_COLUMN                     1
 138 #define ADDR_PAGE                       2
 139 #define ADDR_COLUMN_PAGE                3
 140
 141 #define NAND_ChipID_UNKNOWN             0x00
 142 #define NAND_MAX_FLOORS                 1
 143 #define NAND_MAX_CHIPS                  1
 144 #define NAND_NO_RB                      1
 145 #define CONFIG_SYS_NAND_WP
 146
 147 #define CONFIG_JFFS2_NAND
 148 /* nand device jffs2 lives on */
 149 #define CONFIG_JFFS2_DEV                "nand0"
 150 /* start of jffs2 partition */
 151 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 152 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 153                                                         /* partition */
 154
 155 /* Environment information */
 156 #define CONFIG_BOOTDELAY                10
 157
 158 #define CONFIG_EXTRA_ENV_SETTINGS \
 159         "loadaddr=0x82000000\0" \
 160         "console=ttyS2,115200n8\0" \
 161         "videomode=1024x768@60,vxres=1024,vyres=768\0" \
 162         "videospec=omapfb:vram:2M,vram:4M\0" \
 163         "mmcargs=setenv bootargs console=${console} " \
 164                 "video=${videospec},mode:${videomode} " \
 165                 "root=/dev/mmcblk0p2 rw " \
 166                 "rootfstype=ext3 rootwait\0" \
 167         "nandargs=setenv bootargs console=${console} " \
 168                 "video=${videospec},mode:${videomode} " \
 169                 "root=/dev/mtdblock4 rw " \
 170                 "rootfstype=jffs2\0" \
 171         "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
 172         "bootscript=echo Running bootscript from mmc ...; " \
 173                 "autoscr ${loadaddr}\0" \
 174         "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
 175         "mmcboot=echo Booting from mmc ...; " \
 176                 "run mmcargs; " \
 177                 "bootm ${loadaddr}\0" \
 178         "nandboot=echo Booting from nand ...; " \
 179                 "run nandargs; " \
 180                 "nand read ${loadaddr} 280000 400000; " \
 181                 "bootm ${loadaddr}\0" \
 182
 183 #define CONFIG_BOOTCOMMAND \
 184         "if mmcinit; then " \
 185                 "if run loadbootscript; then " \
 186                         "run bootscript; " \
 187                 "else " \
 188                         "if run loaduimage; then " \
 189                                 "run mmcboot; " \
 190                         "else run nandboot; " \
 191                         "fi; " \
 192                 "fi; " \
 193         "else run nandboot; fi"
 194
 195 #define CONFIG_AUTO_COMPLETE            1
 196 /*
 197  * Miscellaneous configurable options
 198  */
 199 #define V_PROMPT                        "OMAP3 Zoom1# "
 200
 201 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 202 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 203 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 204 #define CONFIG_SYS_PROMPT               V_PROMPT
 205 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 206 /* Print Buffer Size */
 207 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 208                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 209 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 210 /* Boot Argument Buffer Size */
 211 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 212
 213 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 214                                                                 /* works on */
 215 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 216                                         0x01F00000) /* 31MB */
 217
 218 #undef  CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 219
 220 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 221                                                         /* load address */
 222
 223 /*
 224  * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 225  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 226  */
 227 #define V_PVT                           7
 228
 229 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 230 #define CONFIG_SYS_PVT                  V_PVT   /* 2^(pvt+1) */
 231 #define CONFIG_SYS_HZ                   ((V_SCLK) / (2 << CONFIG_SYS_PVT))
 232
 233 /*-----------------------------------------------------------------------
 234  * Stack sizes
 235  *
 236  * The stack sizes are set up in start.S using the settings below
 237  */
 238 #define CONFIG_STACKSIZE        SZ_128K /* regular stack */
 239 #ifdef CONFIG_USE_IRQ
 240 #define CONFIG_STACKSIZE_IRQ    SZ_4K   /* IRQ stack */
 241 #define CONFIG_STACKSIZE_FIQ    SZ_4K   /* FIQ stack */
 242 #endif
 243
 244 /*-----------------------------------------------------------------------
 245  * Physical Memory Map
 246  */
 247 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 248 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 249 #define PHYS_SDRAM_1_SIZE       SZ_32M  /* at least 32 meg */
 250 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 251
 252 /* SDRAM Bank Allocation method */
 253 #define SDRC_R_B_C              1
 254
 255 /*-----------------------------------------------------------------------
 256  * FLASH and environment organization
 257  */
 258
 259 /* **** PISMO SUPPORT *** */
 260
 261 /* Configure the PISMO */
 262 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 263 #define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 264
 265 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors on */
 266                                                 /* one chip */
 267 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 268 #define CONFIG_SYS_MONITOR_LEN          SZ_256K /* Reserve 2 sectors */
 269
 270 #define CONFIG_SYS_FLASH_BASE           boot_flash_base
 271
 272 /* Monitor at start of flash */
 273 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 274 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 275
 276 #define CONFIG_ENV_IS_IN_NAND           1
 277 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 278 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 279
 280 #define CONFIG_SYS_ENV_SECT_SIZE        boot_flash_sec
 281 #define CONFIG_ENV_OFFSET               boot_flash_off
 282 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 283
 284 /*-----------------------------------------------------------------------
 285  * CFI FLASH driver setup
 286  */
 287 /* timeout values are in ticks */
 288 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 289 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 290
 291 /* Flash banks JFFS2 should use */
 292 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 293                                         CONFIG_SYS_MAX_NAND_DEVICE)
 294 #define CONFIG_SYS_JFFS2_MEM_NAND
 295 /* use flash_info[2] */
 296 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 297 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 298
 299 #ifndef __ASSEMBLY__
 300 extern gpmc_csx_t *nand_cs_base;
 301 extern gpmc_t *gpmc_cfg_base;
 302 extern unsigned int boot_flash_base;
 303 extern volatile unsigned int boot_flash_env_addr;
 304 extern unsigned int boot_flash_off;
 305 extern unsigned int boot_flash_sec;
 306 extern unsigned int boot_flash_type;
 307 #endif
 308
 309
 310 #define WRITE_NAND_COMMAND(d, adr)\
 311                         writel(d, &nand_cs_base->nand_cmd)
 312 #define WRITE_NAND_ADDRESS(d, adr)\
 313                         writel(d, &nand_cs_base->nand_adr)
 314 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
 315 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 316
 317 /* Other NAND Access APIs */
 318 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
 319                         while (0)
 320 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
 321                         while (0)
 322 #define NAND_DISABLE_CE(nand)
 323 #define NAND_ENABLE_CE(nand)
 324 #define NAND_WAIT_READY(nand)   udelay(10)
 325
 326 #endif                          /* __CONFIG_H */