2 * (C) Copyright 2003-2004
3 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
6 * Configuation settings for the TI OMAP Perseus 2 board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * If we are developing, we might want to start armboot from ram
33 * so we MUST NOT initialize critical regs like mem-timing ...
36 #define CONFIG_INIT_CRITICAL /* undef for developing */
39 /* allow to overwrite serial and ethaddr */
40 #define CONFIG_ENV_OVERWRITE
44 * High Level Configuration Options
48 #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
49 #define CONFIG_OMAP 1 /* in a TI OMAP core */
50 #define CONFIG_OMAP730 1 /* which is in a 730 */
51 #define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
56 * The OMAP730 Perseus 2 has 13MHz input clock
59 #define CONFIG_SYS_CLK_FREQ 13000000
61 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
63 #define CONFIG_MISC_INIT_R
65 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
66 #define CONFIG_SETUP_MEMORY_TAGS 1
70 * Size of malloc() pool
73 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
74 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
81 #define CONFIG_DRIVER_LAN91C96
82 #define CONFIG_LAN91C96_BASE 0x04000300
83 #define CONFIG_LAN91C96_EXT_PHY
87 * NS16550 Configuration
91 #define CFG_NS16550_SERIAL
92 #define CFG_NS16550_REG_SIZE (1)
93 #define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
94 #define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
98 * select serial console configuration
101 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
104 #define CONFIG_CONS_INDEX 1
105 #define CONFIG_BAUDRATE 115200
106 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
108 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
109 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
112 * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
115 #include <cmd_confdefs.h>
116 #include <configs/omap730.h>
117 #include <configs/h2_p2_dbg_board.h>
119 #define CONFIG_BOOTDELAY 3
120 #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
122 #define CONFIG_LOADADDR 0x10000000
124 #define CONFIG_ETHADDR
125 #define CONFIG_NETMASK 255.255.255.0
126 #define CONFIG_IPADDR 192.168.0.23
127 #define CONFIG_SERVERIP 192.150.0.100
128 #define CONFIG_BOOTFILE "uImage" /* File to load */
130 #if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
131 #define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
132 #define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
137 * Miscellaneous configurable options
140 #define CFG_LONGHELP /* undef to save memory */
141 #define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
142 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
143 /* Print Buffer Size */
144 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
145 #define CFG_MAXARGS 16 /* max number of command args */
146 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
148 #define CFG_MEMTEST_START 0x10000000 /* memtest works on */
149 #define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
151 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
153 #define CFG_LOAD_ADDR 0x10000000 /* default load address */
156 /* The OMAP730 has 3 general purpose MPU timers, they can be driven by
157 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
161 #define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
162 #define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
163 #define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
166 /*-----------------------------------------------------------------------
169 * The stack sizes are set up in start.S using the settings below
172 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
173 #ifdef CONFIG_USE_IRQ
174 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
175 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
179 /*-----------------------------------------------------------------------
180 * Physical Memory Map
183 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
184 #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
185 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
187 #if defined(CONFIG_CS0_BOOT)
188 #define PHYS_FLASH_1 0x0C000000
189 #elif defined(CONFIG_CS3_BOOT)
190 #define PHYS_FLASH_1 0x00000000
192 #error Unknown Boot Chip-Select number
195 #define CFG_FLASH_BASE PHYS_FLASH_1
199 /*-----------------------------------------------------------------------
200 * FLASH and environment organization
203 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
204 #define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
205 #define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
206 /* addr of environment */
207 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
210 /* timeout values are in ticks */
211 #define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
212 #define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
214 #define CFG_ENV_IS_IN_FLASH 1
215 #define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
216 #define CFG_ENV_OFFSET 0x20000 /* environment starts here */
220 #endif /* ! __CONFIG_H */