2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on davinci_dvevm.h. Original Copyrights follow:
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 * SPDX-License-Identifier: GPL-2.0
17 #define CONFIG_DRIVER_TI_EMAC
18 #undef CONFIG_USE_SPIFLASH
19 #undef CONFIG_SYS_USE_NOR
20 #define CONFIG_USE_NAND
25 #define CONFIG_MACH_OMAPL138_LCDK
26 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
27 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
28 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
29 #define CONFIG_SYS_OSCIN_FREQ 24000000
30 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
31 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
32 #define CONFIG_SYS_HZ 1000
33 #define CONFIG_SKIP_LOWLEVEL_INIT
34 #define CONFIG_SYS_TEXT_BASE 0xc1080000
39 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
40 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
41 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
42 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
44 /* memtest start addr */
45 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
47 /* memtest will be run on 16MB */
48 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
50 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
52 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
53 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
54 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
55 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
56 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
57 DAVINCI_SYSCFG_SUSPSRC_I2C)
62 #define CONFIG_SYS_DV_CLKMODE 0
63 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
64 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
65 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
66 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
68 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
69 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
70 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
72 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
73 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
74 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
75 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
77 #define CONFIG_SYS_DA850_PLL0_PLLM 37
78 #define CONFIG_SYS_DA850_PLL1_PLLM 21
81 * DDR2 memory configuration
83 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
84 DV_DDR_PHY_EXT_STRBEN | \
85 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
87 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
88 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
89 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
90 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
91 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
92 (4 << DV_DDR_SDCR_CL_SHIFT) | \
93 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
94 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
96 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
97 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
99 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
100 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
101 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
102 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
103 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
104 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
105 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
106 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
107 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
109 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
110 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
111 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
112 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
113 (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
114 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
115 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
116 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
118 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
119 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
124 #define CONFIG_SYS_NS16550_SERIAL
125 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
126 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
127 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
128 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
129 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132 #define CONFIG_DAVINCI_SPI
133 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
134 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
135 #define CONFIG_SF_DEFAULT_SPEED 30000000
136 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
138 #ifdef CONFIG_USE_SPIFLASH
139 #define CONFIG_SPL_SPI_LOAD
140 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
141 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
147 #define CONFIG_SYS_I2C
148 #define CONFIG_SYS_I2C_DAVINCI
149 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
150 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
151 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
154 * Flash & Environment
156 #ifdef CONFIG_USE_NAND
157 #undef CONFIG_ENV_IS_IN_FLASH
158 #define CONFIG_NAND_DAVINCI
159 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
160 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
161 #define CONFIG_ENV_SIZE (128 << 9)
162 #define CONFIG_SYS_NAND_USE_FLASH_BBT
163 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
164 #define CONFIG_SYS_NAND_PAGE_2K
165 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
166 #define CONFIG_SYS_NAND_CS 3
167 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
168 #define CONFIG_SYS_NAND_MASK_CLE 0x10
169 #define CONFIG_SYS_NAND_MASK_ALE 0x8
170 #undef CONFIG_SYS_NAND_HW_ECC
171 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
172 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
173 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
174 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
175 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
176 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
177 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
178 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
179 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
180 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
181 CONFIG_SYS_NAND_U_BOOT_SIZE - \
182 CONFIG_SYS_MALLOC_LEN - \
183 GENERATED_GBL_DATA_SIZE)
184 #define CONFIG_SYS_NAND_ECCPOS { \
185 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
186 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
187 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
188 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
189 #define CONFIG_SYS_NAND_PAGE_COUNT 64
190 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
191 #define CONFIG_SYS_NAND_ECCSIZE 512
192 #define CONFIG_SYS_NAND_ECCBYTES 10
193 #define CONFIG_SYS_NAND_OOBSIZE 64
194 #define CONFIG_SPL_NAND_BASE
195 #define CONFIG_SPL_NAND_DRIVERS
196 #define CONFIG_SPL_NAND_ECC
197 #define CONFIG_SPL_NAND_SIMPLE
198 #define CONFIG_SPL_NAND_LOAD
201 #ifdef CONFIG_SYS_USE_NOR
202 #define CONFIG_ENV_IS_IN_FLASH
203 #define CONFIG_FLASH_CFI_DRIVER
204 #define CONFIG_SYS_FLASH_CFI
205 #define CONFIG_SYS_FLASH_PROTECTION
206 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
207 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
208 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
209 #define CONFIG_ENV_SIZE (128 << 10)
210 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
211 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
212 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
214 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
217 #ifdef CONFIG_USE_SPIFLASH
218 #undef CONFIG_ENV_IS_IN_FLASH
219 #undef CONFIG_ENV_IS_IN_NAND
220 #define CONFIG_ENV_IS_IN_SPI_FLASH
221 #define CONFIG_ENV_SIZE (64 << 10)
222 #define CONFIG_ENV_OFFSET (256 << 10)
223 #define CONFIG_ENV_SECT_SIZE (64 << 10)
227 * Network & Ethernet Configuration
229 #ifdef CONFIG_DRIVER_TI_EMAC
230 #define CONFIG_EMAC_MDIO_PHY_NUM 7
232 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII
233 #define CONFIG_BOOTP_DEFAULT
234 #define CONFIG_BOOTP_DNS
235 #define CONFIG_BOOTP_DNS2
236 #define CONFIG_BOOTP_SEND_HOSTNAME
237 #define CONFIG_NET_RETRY_COUNT 10
241 * U-Boot general configuration
243 #define CONFIG_MISC_INIT_R
244 #define CONFIG_BOOTFILE "zImage" /* Boot file name */
245 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
246 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
247 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
248 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
249 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
250 #define CONFIG_AUTO_COMPLETE
251 #define CONFIG_CMDLINE_EDITING
252 #define CONFIG_SYS_LONGHELP
253 #define CONFIG_CRC32_VERIFY
254 #define CONFIG_MX_CYCLIC
259 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
260 #define CONFIG_CMDLINE_TAG
261 #define CONFIG_REVISION_TAG
262 #define CONFIG_SETUP_MEMORY_TAGS
263 #define CONFIG_BOOTCOMMAND \
267 #define DEFAULT_LINUX_BOOT_ENV \
268 "loadaddr=0xc0700000\0" \
269 "fdtaddr=0xc0600000\0" \
270 "scriptaddr=0xc0600000\0"
272 #include <environment/ti/mmc.h>
274 #define CONFIG_EXTRA_ENV_SETTINGS \
275 DEFAULT_LINUX_BOOT_ENV \
276 DEFAULT_MMC_TI_ARGS \
279 "bootfile=zImage\0" \
280 "fdtfile=da850-lcdk.dtb\0" \
283 "console=ttyS2,115200n8\0"
288 #define CONFIG_CMD_ENV
289 #define CONFIG_CMD_SAVES
290 #ifdef CONFIG_CMD_BDI
291 #define CONFIG_CLOCKS
294 #ifndef CONFIG_DRIVER_TI_EMAC
297 #ifdef CONFIG_USE_NAND
298 #define CONFIG_CMD_NAND
300 #define CONFIG_CMD_MTDPARTS
301 #define CONFIG_MTD_DEVICE
302 #define CONFIG_MTD_PARTITIONS
304 #define CONFIG_RBTREE
305 #define CONFIG_CMD_UBIFS
308 #if !defined(CONFIG_USE_NAND) && \
309 !defined(CONFIG_SYS_USE_NOR) && \
310 !defined(CONFIG_USE_SPIFLASH)
311 #define CONFIG_ENV_IS_NOWHERE
312 #define CONFIG_ENV_SIZE (16 << 10)
313 #undef CONFIG_CMD_ENV
318 #undef CONFIG_ENV_IS_IN_MMC
321 #ifdef CONFIG_ENV_IS_IN_MMC
322 #undef CONFIG_ENV_SIZE
323 #undef CONFIG_ENV_OFFSET
324 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
325 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
326 #undef CONFIG_ENV_IS_IN_FLASH
327 #undef CONFIG_ENV_IS_IN_NAND
328 #undef CONFIG_ENV_IS_IN_SPI_FLASH
331 #ifndef CONFIG_DIRECT_NOR_BOOT
332 /* defines for SPL */
333 #define CONFIG_SPL_FRAMEWORK
334 #define CONFIG_SPL_BOARD_INIT
335 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
336 CONFIG_SYS_MALLOC_LEN)
337 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
338 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
339 #define CONFIG_SPL_STACK 0x8001ff00
340 #define CONFIG_SPL_TEXT_BASE 0x80000000
341 #define CONFIG_SPL_MAX_FOOTPRINT 32768
342 #define CONFIG_SPL_PAD_TO 32768
345 /* additions for new relocation code, must added to all boards */
346 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
347 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
348 GENERATED_GBL_DATA_SIZE)
349 #endif /* __CONFIG_H */