2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014 Bachmann electronic GmbH
5 * SPDX-License-Identifier: GPL-2.0+
11 #include "mx6_common.h"
13 /* Size of malloc() pool */
14 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
16 #define CONFIG_MISC_INIT_R
19 #define CONFIG_MXC_UART
20 #define CONFIG_MXC_UART_BASE UART1_BASE
23 #define CONFIG_SF_DEFAULT_BUS 2
24 #define CONFIG_SF_DEFAULT_CS 0
25 #define CONFIG_SF_DEFAULT_SPEED 25000000
26 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
29 #define CONFIG_PCA953X
30 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
31 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
34 #define CONFIG_SYS_I2C
35 #define CONFIG_SYS_I2C_MXC
36 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
37 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
38 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
39 #define CONFIG_SYS_I2C_SPEED 100000
42 #define CONFIG_IMX_OTP
43 #define IMX_OTP_BASE OCOTP_BASE_ADDR
44 #define IMX_OTP_ADDR_MAX 0x7F
45 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
46 #define IMX_OTPWRITE_ENABLED
49 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
50 #define CONFIG_SYS_FSL_USDHC_NUM 2
53 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
59 #ifdef CONFIG_CMD_SATA
60 #define CONFIG_SYS_SATA_MAX_DEVICE 1
61 #define CONFIG_DWC_AHSATA_PORT_ID 0
62 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
69 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
72 #define CONFIG_FEC_MXC
74 #define IMX_FEC_BASE ENET_BASE_ADDR
75 #define CONFIG_FEC_XCV_TYPE MII100
76 #define CONFIG_ETHPRIME "FEC"
77 #define CONFIG_FEC_MXC_PHYADDR 0x5
78 #define CONFIG_PHY_SMSC
81 #define CONFIG_ENV_EEPROM_IS_ON_I2C
82 #define CONFIG_SYS_I2C_EEPROM_BUS 1
83 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
84 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
85 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
88 #define CONFIG_PREBOOT ""
91 #define CONFIG_IMX_THERMAL
93 /* Physical Memory Map */
94 #define CONFIG_NR_DRAM_BANKS 1
95 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
97 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
98 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
99 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
101 #define CONFIG_SYS_INIT_SP_OFFSET \
102 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_ADDR \
104 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
106 /* Environment organization */
107 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
108 #define CONFIG_ENV_OFFSET (1024 * 1024)
109 /* M25P16 has an erase size of 64 KiB */
110 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
111 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
112 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
113 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
114 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
116 #define CONFIG_BOOTP_SERVERIP
117 #define CONFIG_BOOTP_BOOTFILE
119 #endif /* __CONFIG_H */