1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * QorIQ RDB boards configuration file
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
19 #define CONFIG_SYS_L2_SIZE (256 << 10)
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
45 * P1020RDB-PD board has user selectable switches for evaluating different
46 * frequency and boot options for the P1020 device. The table that
47 * follow describe the available options. The front six binary number was in
48 * accordance with SW3[1:6].
49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
70 * Dynamic MTD Partition support with mtdparts
72 #define CONFIG_MTD_DEVICE
73 #define CONFIG_MTD_PARTITIONS
74 #define CONFIG_FLASH_CFI_MTD
77 #if defined(CONFIG_TARGET_P1021RDB)
78 #define CONFIG_BOARDNAME "P1021RDB-PC"
79 #define CONFIG_NAND_FSL_ELBC
81 #define CONFIG_VSC7385_ENET
82 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
83 addresses in the LBC */
84 #define __SW_BOOT_MASK 0x03
85 #define __SW_BOOT_NOR 0x5c
86 #define __SW_BOOT_SPI 0x1c
87 #define __SW_BOOT_SD 0x9c
88 #define __SW_BOOT_NAND 0xec
89 #define __SW_BOOT_PCIE 0x6c
90 #define CONFIG_SYS_L2_SIZE (256 << 10)
92 * Dynamic MTD Partition support with mtdparts
94 #define CONFIG_MTD_DEVICE
95 #define CONFIG_MTD_PARTITIONS
96 #define CONFIG_FLASH_CFI_MTD
99 #if defined(CONFIG_TARGET_P1024RDB)
100 #define CONFIG_BOARDNAME "P1024RDB"
101 #define CONFIG_NAND_FSL_ELBC
103 #define __SW_BOOT_MASK 0xf3
104 #define __SW_BOOT_NOR 0x00
105 #define __SW_BOOT_SPI 0x08
106 #define __SW_BOOT_SD 0x04
107 #define __SW_BOOT_NAND 0x0c
108 #define CONFIG_SYS_L2_SIZE (256 << 10)
111 #if defined(CONFIG_TARGET_P1025RDB)
112 #define CONFIG_BOARDNAME "P1025RDB"
113 #define CONFIG_NAND_FSL_ELBC
117 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
118 addresses in the LBC */
119 #define __SW_BOOT_MASK 0xf3
120 #define __SW_BOOT_NOR 0x00
121 #define __SW_BOOT_SPI 0x08
122 #define __SW_BOOT_SD 0x04
123 #define __SW_BOOT_NAND 0x0c
124 #define CONFIG_SYS_L2_SIZE (256 << 10)
127 #if defined(CONFIG_TARGET_P2020RDB)
128 #define CONFIG_BOARDNAME "P2020RDB-PC"
129 #define CONFIG_NAND_FSL_ELBC
130 #define CONFIG_VSC7385_ENET
131 #define __SW_BOOT_MASK 0x03
132 #define __SW_BOOT_NOR 0xc8
133 #define __SW_BOOT_SPI 0x28
134 #define __SW_BOOT_SD 0x68 /* or 0x18 */
135 #define __SW_BOOT_NAND 0xe8
136 #define __SW_BOOT_PCIE 0xa8
137 #define CONFIG_SYS_L2_SIZE (512 << 10)
139 * Dynamic MTD Partition support with mtdparts
141 #define CONFIG_MTD_DEVICE
142 #define CONFIG_MTD_PARTITIONS
143 #define CONFIG_FLASH_CFI_MTD
147 #define CONFIG_SPL_FLUSH_IMAGE
148 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
149 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
150 #define CONFIG_SPL_PAD_TO 0x20000
151 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
152 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
153 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
154 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
155 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
156 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
157 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
158 #define CONFIG_SPL_MMC_BOOT
159 #ifdef CONFIG_SPL_BUILD
160 #define CONFIG_SPL_COMMON_INIT_DDR
164 #ifdef CONFIG_SPIFLASH
165 #define CONFIG_SPL_SPI_FLASH_MINIMAL
166 #define CONFIG_SPL_FLUSH_IMAGE
167 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
168 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
169 #define CONFIG_SPL_PAD_TO 0x20000
170 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
171 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
172 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
173 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
174 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
175 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
176 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
177 #define CONFIG_SPL_SPI_BOOT
178 #ifdef CONFIG_SPL_BUILD
179 #define CONFIG_SPL_COMMON_INIT_DDR
184 #ifdef CONFIG_TPL_BUILD
185 #define CONFIG_SPL_NAND_BOOT
186 #define CONFIG_SPL_FLUSH_IMAGE
187 #define CONFIG_SPL_NAND_INIT
188 #define CONFIG_SPL_COMMON_INIT_DDR
189 #define CONFIG_SPL_MAX_SIZE (128 << 10)
190 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
191 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
192 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
193 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
194 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
195 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
196 #elif defined(CONFIG_SPL_BUILD)
197 #define CONFIG_SPL_INIT_MINIMAL
198 #define CONFIG_SPL_FLUSH_IMAGE
199 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
200 #define CONFIG_SPL_TEXT_BASE 0xff800000
201 #define CONFIG_SPL_MAX_SIZE 4096
202 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
203 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
204 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
205 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
206 #endif /* not CONFIG_TPL_BUILD */
208 #define CONFIG_SPL_PAD_TO 0x20000
209 #define CONFIG_TPL_PAD_TO 0x20000
210 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
211 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
214 #ifndef CONFIG_RESET_VECTOR_ADDRESS
215 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
218 #ifndef CONFIG_SYS_MONITOR_BASE
219 #ifdef CONFIG_SPL_BUILD
220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
228 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
229 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
230 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
231 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
232 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
233 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
235 #define CONFIG_ENV_OVERWRITE
237 #define CONFIG_SYS_SATA_MAX_DEVICE 2
240 #if defined(CONFIG_TARGET_P2020RDB)
241 #define CONFIG_SYS_CLK_FREQ 100000000
243 #define CONFIG_SYS_CLK_FREQ 66666666
245 #define CONFIG_DDR_CLK_FREQ 66666666
247 #define CONFIG_HWCONFIG
249 * These can be toggled for performance analysis, otherwise use default.
251 #define CONFIG_L2_CACHE
254 #define CONFIG_ENABLE_36BIT_PHYS
256 #ifdef CONFIG_PHYS_64BIT
257 #define CONFIG_ADDR_MAP 1
258 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
261 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
262 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
264 #define CONFIG_SYS_CCSRBAR 0xffe00000
265 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
267 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
269 #ifdef CONFIG_SPL_BUILD
270 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
274 #define CONFIG_SYS_DDR_RAW_TIMING
275 #define CONFIG_DDR_SPD
276 #define CONFIG_SYS_SPD_BUS_NUM 1
277 #define SPD_EEPROM_ADDRESS 0x52
278 #undef CONFIG_FSL_DDR_INTERACTIVE
280 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
281 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
282 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
284 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
285 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
287 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
288 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
289 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
291 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
293 /* Default settings for DDR3 */
294 #ifndef CONFIG_TARGET_P2020RDB
295 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
296 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
297 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
298 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
299 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
300 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
302 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
303 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
304 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
305 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
307 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
308 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
309 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
310 #define CONFIG_SYS_DDR_RCW_1 0x00000000
311 #define CONFIG_SYS_DDR_RCW_2 0x00000000
312 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
313 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
314 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
315 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
317 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
318 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
319 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
320 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
321 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
322 #define CONFIG_SYS_DDR_MODE_1 0x40461520
323 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
324 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
327 #undef CONFIG_CLOCKS_IN_MHZ
332 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
333 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
334 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
335 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
337 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
338 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
339 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
340 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
341 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
342 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
343 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
347 * Local Bus Definitions
349 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
350 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
351 #define CONFIG_SYS_FLASH_BASE 0xec000000
352 #elif defined(CONFIG_TARGET_P1020UTM)
353 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
354 #define CONFIG_SYS_FLASH_BASE 0xee000000
356 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
357 #define CONFIG_SYS_FLASH_BASE 0xef000000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
363 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
366 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
369 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
371 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
372 #define CONFIG_SYS_FLASH_QUIET_TEST
373 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
375 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
377 #undef CONFIG_SYS_FLASH_CHECKSUM
378 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
379 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
381 #define CONFIG_FLASH_CFI_DRIVER
382 #define CONFIG_SYS_FLASH_CFI
383 #define CONFIG_SYS_FLASH_EMPTY_INFO
384 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
387 #ifdef CONFIG_NAND_FSL_ELBC
388 #define CONFIG_SYS_NAND_BASE 0xff800000
389 #ifdef CONFIG_PHYS_64BIT
390 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
392 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
395 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
396 #define CONFIG_SYS_MAX_NAND_DEVICE 1
397 #if defined(CONFIG_TARGET_P1020RDB_PD)
398 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
400 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
403 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
404 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
405 | BR_PS_8 /* Port Size = 8 bit */ \
406 | BR_MS_FCM /* MSEL = FCM */ \
408 #if defined(CONFIG_TARGET_P1020RDB_PD)
409 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
410 | OR_FCM_PGS /* Large Page*/ \
418 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
426 #endif /* CONFIG_NAND_FSL_ELBC */
428 #define CONFIG_SYS_INIT_RAM_LOCK
429 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
430 #ifdef CONFIG_PHYS_64BIT
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
433 /* The assembler doesn't like typecast */
434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
435 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
436 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
438 /* Initial L1 address */
439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
443 /* Size of used area in RAM */
444 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
446 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
447 GENERATED_GBL_DATA_SIZE)
448 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
450 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
451 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
453 #define CONFIG_SYS_CPLD_BASE 0xffa00000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
457 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
459 /* CPLD config size: 1Mb */
460 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
462 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
464 #define CONFIG_SYS_PMC_BASE 0xff980000
465 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
466 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
468 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
469 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
473 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
474 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
475 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
476 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
478 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
479 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
480 #ifdef CONFIG_NAND_FSL_ELBC
481 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
482 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
485 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
486 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
489 #ifdef CONFIG_VSC7385_ENET
490 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
492 #ifdef CONFIG_PHYS_64BIT
493 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
495 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
498 #define CONFIG_SYS_VSC7385_BR_PRELIM \
499 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
500 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
501 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
502 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
504 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
505 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
507 /* The size of the VSC7385 firmware image */
508 #define CONFIG_VSC7385_IMAGE_SIZE 8192
512 * Config the L2 Cache as L2 SRAM
514 #if defined(CONFIG_SPL_BUILD)
515 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
516 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
517 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
518 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
519 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
520 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
521 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
522 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
523 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
524 #if defined(CONFIG_TARGET_P2020RDB)
525 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
527 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
529 #elif defined(CONFIG_NAND)
530 #ifdef CONFIG_TPL_BUILD
531 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
532 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
533 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
534 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
535 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
536 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
537 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
538 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
540 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
541 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
542 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
543 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
544 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
545 #endif /* CONFIG_TPL_BUILD */
549 /* Serial Port - controlled on board with jumper J8
553 #undef CONFIG_SERIAL_SOFTWARE_FIFO
554 #define CONFIG_SYS_NS16550_SERIAL
555 #define CONFIG_SYS_NS16550_REG_SIZE 1
556 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
557 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
558 #define CONFIG_NS16550_MIN_FUNCTIONS
561 #define CONFIG_SYS_BAUDRATE_TABLE \
562 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
564 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
565 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
568 #define CONFIG_SYS_I2C
569 #define CONFIG_SYS_I2C_FSL
570 #define CONFIG_SYS_FSL_I2C_SPEED 400000
571 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
572 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
573 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
574 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
575 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
576 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
577 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
578 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
583 #undef CONFIG_ID_EEPROM
585 #define CONFIG_RTC_PT7C4338
586 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
587 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
589 /* enable read and write access to EEPROM */
590 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
591 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
592 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
595 * eSPI - Enhanced SPI
597 #define CONFIG_HARD_SPI
599 #if defined(CONFIG_SPI_FLASH)
600 #define CONFIG_SF_DEFAULT_SPEED 10000000
601 #define CONFIG_SF_DEFAULT_MODE 0
604 #if defined(CONFIG_PCI)
607 * Memory space is mapped 1-1, but I/O space must start from 0.
610 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
611 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
612 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
613 #ifdef CONFIG_PHYS_64BIT
614 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
615 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
617 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
618 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
620 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
621 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
622 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
623 #ifdef CONFIG_PHYS_64BIT
624 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
626 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
628 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
630 /* controller 1, Slot 2, tgtid 1, Base address a000 */
631 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
632 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
633 #ifdef CONFIG_PHYS_64BIT
634 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
635 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
637 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
638 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
640 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
641 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
642 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
643 #ifdef CONFIG_PHYS_64BIT
644 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
646 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
648 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
650 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
651 #endif /* CONFIG_PCI */
653 #if defined(CONFIG_TSEC_ENET)
654 #define CONFIG_MII /* MII PHY management */
656 #define CONFIG_TSEC1_NAME "eTSEC1"
658 #define CONFIG_TSEC2_NAME "eTSEC2"
660 #define CONFIG_TSEC3_NAME "eTSEC3"
662 #define TSEC1_PHY_ADDR 2
663 #define TSEC2_PHY_ADDR 0
664 #define TSEC3_PHY_ADDR 1
666 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
667 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
668 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
670 #define TSEC1_PHYIDX 0
671 #define TSEC2_PHYIDX 0
672 #define TSEC3_PHYIDX 0
674 #define CONFIG_ETHPRIME "eTSEC1"
676 #define CONFIG_HAS_ETH0
677 #define CONFIG_HAS_ETH1
678 #define CONFIG_HAS_ETH2
679 #endif /* CONFIG_TSEC_ENET */
682 /* QE microcode/firmware address */
683 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
684 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
685 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
686 #endif /* CONFIG_QE */
688 #ifdef CONFIG_TARGET_P1025RDB
690 * QE UEC ethernet configuration
692 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
694 #undef CONFIG_UEC_ETH
695 #define CONFIG_PHY_MODE_NEED_CHANGE
697 #define CONFIG_UEC_ETH1 /* ETH1 */
698 #define CONFIG_HAS_ETH0
700 #ifdef CONFIG_UEC_ETH1
701 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
702 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
703 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
704 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
705 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
706 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
707 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
708 #endif /* CONFIG_UEC_ETH1 */
710 #define CONFIG_UEC_ETH5 /* ETH5 */
711 #define CONFIG_HAS_ETH1
713 #ifdef CONFIG_UEC_ETH5
714 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
715 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
716 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
717 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
718 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
719 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
720 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
721 #endif /* CONFIG_UEC_ETH5 */
722 #endif /* CONFIG_TARGET_P1025RDB */
727 #ifdef CONFIG_SPIFLASH
728 #define CONFIG_ENV_SPI_BUS 0
729 #define CONFIG_ENV_SPI_CS 0
730 #define CONFIG_ENV_SPI_MAX_HZ 10000000
731 #define CONFIG_ENV_SPI_MODE 0
732 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
733 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
734 #define CONFIG_ENV_SECT_SIZE 0x10000
735 #elif defined(CONFIG_SDCARD)
736 #define CONFIG_FSL_FIXED_MMC_LOCATION
737 #define CONFIG_ENV_SIZE 0x2000
738 #define CONFIG_SYS_MMC_ENV_DEV 0
739 #elif defined(CONFIG_NAND)
740 #ifdef CONFIG_TPL_BUILD
741 #define CONFIG_ENV_SIZE 0x2000
742 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
744 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
746 #define CONFIG_ENV_OFFSET (1024 * 1024)
747 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
748 #elif defined(CONFIG_SYS_RAMBOOT)
749 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
750 #define CONFIG_ENV_SIZE 0x2000
752 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
753 #define CONFIG_ENV_SIZE 0x2000
754 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
757 #define CONFIG_LOADS_ECHO /* echo on for serial download */
758 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
763 #define CONFIG_HAS_FSL_DR_USB
765 #if defined(CONFIG_HAS_FSL_DR_USB)
766 #ifdef CONFIG_USB_EHCI_HCD
767 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
768 #define CONFIG_USB_EHCI_FSL
769 #define CONFIG_EHCI_DESC_BIG_ENDIAN
773 #if defined(CONFIG_TARGET_P1020RDB_PD)
774 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
778 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
781 #undef CONFIG_WATCHDOG /* watchdog disabled */
784 * Miscellaneous configurable options
786 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
789 * For booting Linux, the board info and command line data
790 * have to be in the first 64 MB of memory, since this is
791 * the maximum mapped by the Linux kernel during initialization.
793 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
794 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
796 #if defined(CONFIG_CMD_KGDB)
797 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
801 * Environment Configuration
803 #define CONFIG_HOSTNAME "unknown"
804 #define CONFIG_ROOTPATH "/opt/nfsroot"
805 #define CONFIG_BOOTFILE "uImage"
806 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
808 /* default location for tftp and bootm */
809 #define CONFIG_LOADADDR 1000000
812 #define __NOR_RST_CMD \
813 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
814 i2c mw 18 3 __SW_BOOT_MASK 1; reset
817 #define __SPI_RST_CMD \
818 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
819 i2c mw 18 3 __SW_BOOT_MASK 1; reset
822 #define __SD_RST_CMD \
823 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
824 i2c mw 18 3 __SW_BOOT_MASK 1; reset
826 #ifdef __SW_BOOT_NAND
827 #define __NAND_RST_CMD \
828 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
829 i2c mw 18 3 __SW_BOOT_MASK 1; reset
831 #ifdef __SW_BOOT_PCIE
832 #define __PCIE_RST_CMD \
833 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
834 i2c mw 18 3 __SW_BOOT_MASK 1; reset
837 #define CONFIG_EXTRA_ENV_SETTINGS \
839 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
840 "loadaddr=1000000\0" \
841 "bootfile=uImage\0" \
842 "tftpflash=tftpboot $loadaddr $uboot; " \
843 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
844 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
845 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
846 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
847 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
848 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
849 "consoledev=ttyS0\0" \
850 "ramdiskaddr=2000000\0" \
851 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
852 "fdtaddr=1e00000\0" \
854 "jffs2nor=mtdblock3\0" \
855 "norbootaddr=ef080000\0" \
856 "norfdtaddr=ef040000\0" \
857 "jffs2nand=mtdblock9\0" \
858 "nandbootaddr=100000\0" \
859 "nandfdtaddr=80000\0" \
860 "ramdisk_size=120000\0" \
861 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
862 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
863 __stringify(__NOR_RST_CMD)"\0" \
864 __stringify(__SPI_RST_CMD)"\0" \
865 __stringify(__SD_RST_CMD)"\0" \
866 __stringify(__NAND_RST_CMD)"\0" \
867 __stringify(__PCIE_RST_CMD)"\0"
869 #define CONFIG_NFSBOOTCOMMAND \
870 "setenv bootargs root=/dev/nfs rw " \
871 "nfsroot=$serverip:$rootpath " \
872 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
873 "console=$consoledev,$baudrate $othbootargs;" \
874 "tftp $loadaddr $bootfile;" \
875 "tftp $fdtaddr $fdtfile;" \
876 "bootm $loadaddr - $fdtaddr"
878 #define CONFIG_HDBOOT \
879 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
880 "console=$consoledev,$baudrate $othbootargs;" \
882 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
883 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
884 "bootm $loadaddr - $fdtaddr"
886 #define CONFIG_USB_FAT_BOOT \
887 "setenv bootargs root=/dev/ram rw " \
888 "console=$consoledev,$baudrate $othbootargs " \
889 "ramdisk_size=$ramdisk_size;" \
891 "fatload usb 0:2 $loadaddr $bootfile;" \
892 "fatload usb 0:2 $fdtaddr $fdtfile;" \
893 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
894 "bootm $loadaddr $ramdiskaddr $fdtaddr"
896 #define CONFIG_USB_EXT2_BOOT \
897 "setenv bootargs root=/dev/ram rw " \
898 "console=$consoledev,$baudrate $othbootargs " \
899 "ramdisk_size=$ramdisk_size;" \
901 "ext2load usb 0:4 $loadaddr $bootfile;" \
902 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
903 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
904 "bootm $loadaddr $ramdiskaddr $fdtaddr"
906 #define CONFIG_NORBOOT \
907 "setenv bootargs root=/dev/$jffs2nor rw " \
908 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
909 "bootm $norbootaddr - $norfdtaddr"
911 #define CONFIG_RAMBOOTCOMMAND \
912 "setenv bootargs root=/dev/ram rw " \
913 "console=$consoledev,$baudrate $othbootargs " \
914 "ramdisk_size=$ramdisk_size;" \
915 "tftp $ramdiskaddr $ramdiskfile;" \
916 "tftp $loadaddr $bootfile;" \
917 "tftp $fdtaddr $fdtfile;" \
918 "bootm $loadaddr $ramdiskaddr $fdtaddr"
920 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
922 #endif /* __CONFIG_H */