2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_FLASH_CFI_MTD
78 #if defined(CONFIG_TARGET_P1021RDB)
79 #define CONFIG_BOARDNAME "P1021RDB-PC"
80 #define CONFIG_NAND_FSL_ELBC
82 #define CONFIG_VSC7385_ENET
83 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
84 addresses in the LBC */
85 #define __SW_BOOT_MASK 0x03
86 #define __SW_BOOT_NOR 0x5c
87 #define __SW_BOOT_SPI 0x1c
88 #define __SW_BOOT_SD 0x9c
89 #define __SW_BOOT_NAND 0xec
90 #define __SW_BOOT_PCIE 0x6c
91 #define CONFIG_SYS_L2_SIZE (256 << 10)
93 * Dynamic MTD Partition support with mtdparts
95 #define CONFIG_MTD_DEVICE
96 #define CONFIG_MTD_PARTITIONS
97 #define CONFIG_FLASH_CFI_MTD
100 #if defined(CONFIG_TARGET_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
104 #define __SW_BOOT_MASK 0xf3
105 #define __SW_BOOT_NOR 0x00
106 #define __SW_BOOT_SPI 0x08
107 #define __SW_BOOT_SD 0x04
108 #define __SW_BOOT_NAND 0x0c
109 #define CONFIG_SYS_L2_SIZE (256 << 10)
112 #if defined(CONFIG_TARGET_P1025RDB)
113 #define CONFIG_BOARDNAME "P1025RDB"
114 #define CONFIG_NAND_FSL_ELBC
118 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
119 addresses in the LBC */
120 #define __SW_BOOT_MASK 0xf3
121 #define __SW_BOOT_NOR 0x00
122 #define __SW_BOOT_SPI 0x08
123 #define __SW_BOOT_SD 0x04
124 #define __SW_BOOT_NAND 0x0c
125 #define CONFIG_SYS_L2_SIZE (256 << 10)
128 #if defined(CONFIG_TARGET_P2020RDB)
129 #define CONFIG_BOARDNAME "P2020RDB-PC"
130 #define CONFIG_NAND_FSL_ELBC
131 #define CONFIG_VSC7385_ENET
132 #define __SW_BOOT_MASK 0x03
133 #define __SW_BOOT_NOR 0xc8
134 #define __SW_BOOT_SPI 0x28
135 #define __SW_BOOT_SD 0x68 /* or 0x18 */
136 #define __SW_BOOT_NAND 0xe8
137 #define __SW_BOOT_PCIE 0xa8
138 #define CONFIG_SYS_L2_SIZE (512 << 10)
140 * Dynamic MTD Partition support with mtdparts
142 #define CONFIG_MTD_DEVICE
143 #define CONFIG_MTD_PARTITIONS
144 #define CONFIG_FLASH_CFI_MTD
148 #define CONFIG_SPL_FLUSH_IMAGE
149 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
150 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
151 #define CONFIG_SPL_PAD_TO 0x20000
152 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
153 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
154 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
155 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
156 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
157 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
158 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
159 #define CONFIG_SPL_MMC_BOOT
160 #ifdef CONFIG_SPL_BUILD
161 #define CONFIG_SPL_COMMON_INIT_DDR
165 #ifdef CONFIG_SPIFLASH
166 #define CONFIG_SPL_SPI_FLASH_MINIMAL
167 #define CONFIG_SPL_FLUSH_IMAGE
168 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
169 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
170 #define CONFIG_SPL_PAD_TO 0x20000
171 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
172 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
173 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
174 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
177 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
178 #define CONFIG_SPL_SPI_BOOT
179 #ifdef CONFIG_SPL_BUILD
180 #define CONFIG_SPL_COMMON_INIT_DDR
185 #ifdef CONFIG_TPL_BUILD
186 #define CONFIG_SPL_NAND_BOOT
187 #define CONFIG_SPL_FLUSH_IMAGE
188 #define CONFIG_SPL_NAND_INIT
189 #define CONFIG_SPL_COMMON_INIT_DDR
190 #define CONFIG_SPL_MAX_SIZE (128 << 10)
191 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
192 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
193 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
194 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
195 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
196 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
197 #elif defined(CONFIG_SPL_BUILD)
198 #define CONFIG_SPL_INIT_MINIMAL
199 #define CONFIG_SPL_FLUSH_IMAGE
200 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
201 #define CONFIG_SPL_TEXT_BASE 0xff800000
202 #define CONFIG_SPL_MAX_SIZE 4096
203 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
204 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
205 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
206 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
207 #endif /* not CONFIG_TPL_BUILD */
209 #define CONFIG_SPL_PAD_TO 0x20000
210 #define CONFIG_TPL_PAD_TO 0x20000
211 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
212 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
215 #ifndef CONFIG_RESET_VECTOR_ADDRESS
216 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
219 #ifndef CONFIG_SYS_MONITOR_BASE
220 #ifdef CONFIG_SPL_BUILD
221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
229 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
230 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
231 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
232 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
233 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
234 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
236 #define CONFIG_ENV_OVERWRITE
238 #define CONFIG_SYS_SATA_MAX_DEVICE 2
241 #if defined(CONFIG_TARGET_P2020RDB)
242 #define CONFIG_SYS_CLK_FREQ 100000000
244 #define CONFIG_SYS_CLK_FREQ 66666666
246 #define CONFIG_DDR_CLK_FREQ 66666666
248 #define CONFIG_HWCONFIG
250 * These can be toggled for performance analysis, otherwise use default.
252 #define CONFIG_L2_CACHE
255 #define CONFIG_ENABLE_36BIT_PHYS
257 #ifdef CONFIG_PHYS_64BIT
258 #define CONFIG_ADDR_MAP 1
259 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
262 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
263 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
265 #define CONFIG_SYS_CCSRBAR 0xffe00000
266 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
268 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
270 #ifdef CONFIG_SPL_BUILD
271 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
275 #define CONFIG_SYS_DDR_RAW_TIMING
276 #define CONFIG_DDR_SPD
277 #define CONFIG_SYS_SPD_BUS_NUM 1
278 #define SPD_EEPROM_ADDRESS 0x52
279 #undef CONFIG_FSL_DDR_INTERACTIVE
281 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
282 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
283 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
285 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
286 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
288 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
289 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
290 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
292 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
294 /* Default settings for DDR3 */
295 #ifndef CONFIG_TARGET_P2020RDB
296 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
297 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
298 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
299 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
300 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
301 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
303 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
304 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
305 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
306 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
308 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
309 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
310 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
311 #define CONFIG_SYS_DDR_RCW_1 0x00000000
312 #define CONFIG_SYS_DDR_RCW_2 0x00000000
313 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
314 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
315 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
316 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
318 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
319 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
320 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
321 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
322 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
323 #define CONFIG_SYS_DDR_MODE_1 0x40461520
324 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
325 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
328 #undef CONFIG_CLOCKS_IN_MHZ
333 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
334 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
335 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
336 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
338 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
339 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
340 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
341 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
342 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
343 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
344 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
348 * Local Bus Definitions
350 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
351 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
352 #define CONFIG_SYS_FLASH_BASE 0xec000000
353 #elif defined(CONFIG_TARGET_P1020UTM)
354 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
355 #define CONFIG_SYS_FLASH_BASE 0xee000000
357 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
358 #define CONFIG_SYS_FLASH_BASE 0xef000000
361 #ifdef CONFIG_PHYS_64BIT
362 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
364 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
367 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
370 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
372 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
373 #define CONFIG_SYS_FLASH_QUIET_TEST
374 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
376 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
378 #undef CONFIG_SYS_FLASH_CHECKSUM
379 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
380 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
382 #define CONFIG_FLASH_CFI_DRIVER
383 #define CONFIG_SYS_FLASH_CFI
384 #define CONFIG_SYS_FLASH_EMPTY_INFO
385 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
388 #ifdef CONFIG_NAND_FSL_ELBC
389 #define CONFIG_SYS_NAND_BASE 0xff800000
390 #ifdef CONFIG_PHYS_64BIT
391 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
393 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
396 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
397 #define CONFIG_SYS_MAX_NAND_DEVICE 1
398 #if defined(CONFIG_TARGET_P1020RDB_PD)
399 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
401 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
404 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
405 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
406 | BR_PS_8 /* Port Size = 8 bit */ \
407 | BR_MS_FCM /* MSEL = FCM */ \
409 #if defined(CONFIG_TARGET_P1020RDB_PD)
410 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
411 | OR_FCM_PGS /* Large Page*/ \
419 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
427 #endif /* CONFIG_NAND_FSL_ELBC */
429 #define CONFIG_SYS_INIT_RAM_LOCK
430 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
431 #ifdef CONFIG_PHYS_64BIT
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
434 /* The assembler doesn't like typecast */
435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
436 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
437 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
439 /* Initial L1 address */
440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
444 /* Size of used area in RAM */
445 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
447 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
448 GENERATED_GBL_DATA_SIZE)
449 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
451 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
452 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
454 #define CONFIG_SYS_CPLD_BASE 0xffa00000
455 #ifdef CONFIG_PHYS_64BIT
456 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
458 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
460 /* CPLD config size: 1Mb */
461 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
463 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
465 #define CONFIG_SYS_PMC_BASE 0xff980000
466 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
467 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
469 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
470 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
474 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
475 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
476 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
477 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
479 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
480 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
481 #ifdef CONFIG_NAND_FSL_ELBC
482 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
483 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
486 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
487 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
490 #ifdef CONFIG_VSC7385_ENET
491 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
493 #ifdef CONFIG_PHYS_64BIT
494 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
496 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
499 #define CONFIG_SYS_VSC7385_BR_PRELIM \
500 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
501 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
502 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
503 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
505 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
506 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
508 /* The size of the VSC7385 firmware image */
509 #define CONFIG_VSC7385_IMAGE_SIZE 8192
513 * Config the L2 Cache as L2 SRAM
515 #if defined(CONFIG_SPL_BUILD)
516 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
517 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
518 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
519 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
520 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
521 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
522 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
523 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
524 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
525 #if defined(CONFIG_TARGET_P2020RDB)
526 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
528 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
530 #elif defined(CONFIG_NAND)
531 #ifdef CONFIG_TPL_BUILD
532 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
533 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
534 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
535 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
536 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
537 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
538 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
539 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
541 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
542 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
543 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
544 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
545 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
546 #endif /* CONFIG_TPL_BUILD */
550 /* Serial Port - controlled on board with jumper J8
554 #undef CONFIG_SERIAL_SOFTWARE_FIFO
555 #define CONFIG_SYS_NS16550_SERIAL
556 #define CONFIG_SYS_NS16550_REG_SIZE 1
557 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
558 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
559 #define CONFIG_NS16550_MIN_FUNCTIONS
562 #define CONFIG_SYS_BAUDRATE_TABLE \
563 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
565 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
566 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
569 #define CONFIG_SYS_I2C
570 #define CONFIG_SYS_I2C_FSL
571 #define CONFIG_SYS_FSL_I2C_SPEED 400000
572 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
573 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
574 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
575 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
576 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
577 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
578 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
579 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
584 #undef CONFIG_ID_EEPROM
586 #define CONFIG_RTC_PT7C4338
587 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
588 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
590 /* enable read and write access to EEPROM */
591 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
592 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
593 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
596 * eSPI - Enhanced SPI
598 #define CONFIG_HARD_SPI
600 #if defined(CONFIG_SPI_FLASH)
601 #define CONFIG_SF_DEFAULT_SPEED 10000000
602 #define CONFIG_SF_DEFAULT_MODE 0
605 #if defined(CONFIG_PCI)
608 * Memory space is mapped 1-1, but I/O space must start from 0.
611 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
612 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
613 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
614 #ifdef CONFIG_PHYS_64BIT
615 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
616 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
618 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
619 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
621 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
622 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
623 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
624 #ifdef CONFIG_PHYS_64BIT
625 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
627 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
629 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
631 /* controller 1, Slot 2, tgtid 1, Base address a000 */
632 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
633 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
634 #ifdef CONFIG_PHYS_64BIT
635 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
636 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
638 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
639 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
641 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
642 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
643 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
644 #ifdef CONFIG_PHYS_64BIT
645 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
647 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
649 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
651 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
652 #endif /* CONFIG_PCI */
654 #if defined(CONFIG_TSEC_ENET)
655 #define CONFIG_MII /* MII PHY management */
657 #define CONFIG_TSEC1_NAME "eTSEC1"
659 #define CONFIG_TSEC2_NAME "eTSEC2"
661 #define CONFIG_TSEC3_NAME "eTSEC3"
663 #define TSEC1_PHY_ADDR 2
664 #define TSEC2_PHY_ADDR 0
665 #define TSEC3_PHY_ADDR 1
667 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
668 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
669 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
671 #define TSEC1_PHYIDX 0
672 #define TSEC2_PHYIDX 0
673 #define TSEC3_PHYIDX 0
675 #define CONFIG_ETHPRIME "eTSEC1"
677 #define CONFIG_HAS_ETH0
678 #define CONFIG_HAS_ETH1
679 #define CONFIG_HAS_ETH2
680 #endif /* CONFIG_TSEC_ENET */
683 /* QE microcode/firmware address */
684 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
685 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
686 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
687 #endif /* CONFIG_QE */
689 #ifdef CONFIG_TARGET_P1025RDB
691 * QE UEC ethernet configuration
693 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
695 #undef CONFIG_UEC_ETH
696 #define CONFIG_PHY_MODE_NEED_CHANGE
698 #define CONFIG_UEC_ETH1 /* ETH1 */
699 #define CONFIG_HAS_ETH0
701 #ifdef CONFIG_UEC_ETH1
702 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
703 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
704 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
705 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
706 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
707 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
708 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
709 #endif /* CONFIG_UEC_ETH1 */
711 #define CONFIG_UEC_ETH5 /* ETH5 */
712 #define CONFIG_HAS_ETH1
714 #ifdef CONFIG_UEC_ETH5
715 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
716 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
717 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
718 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
719 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
720 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
721 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
722 #endif /* CONFIG_UEC_ETH5 */
723 #endif /* CONFIG_TARGET_P1025RDB */
728 #ifdef CONFIG_SPIFLASH
729 #define CONFIG_ENV_SPI_BUS 0
730 #define CONFIG_ENV_SPI_CS 0
731 #define CONFIG_ENV_SPI_MAX_HZ 10000000
732 #define CONFIG_ENV_SPI_MODE 0
733 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
734 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
735 #define CONFIG_ENV_SECT_SIZE 0x10000
736 #elif defined(CONFIG_SDCARD)
737 #define CONFIG_FSL_FIXED_MMC_LOCATION
738 #define CONFIG_ENV_SIZE 0x2000
739 #define CONFIG_SYS_MMC_ENV_DEV 0
740 #elif defined(CONFIG_NAND)
741 #ifdef CONFIG_TPL_BUILD
742 #define CONFIG_ENV_SIZE 0x2000
743 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
745 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
747 #define CONFIG_ENV_OFFSET (1024 * 1024)
748 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
749 #elif defined(CONFIG_SYS_RAMBOOT)
750 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
751 #define CONFIG_ENV_SIZE 0x2000
753 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
754 #define CONFIG_ENV_SIZE 0x2000
755 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
758 #define CONFIG_LOADS_ECHO /* echo on for serial download */
759 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
764 #define CONFIG_HAS_FSL_DR_USB
766 #if defined(CONFIG_HAS_FSL_DR_USB)
767 #ifdef CONFIG_USB_EHCI_HCD
768 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
769 #define CONFIG_USB_EHCI_FSL
770 #define CONFIG_EHCI_DESC_BIG_ENDIAN
774 #if defined(CONFIG_TARGET_P1020RDB_PD)
775 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
779 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
782 #undef CONFIG_WATCHDOG /* watchdog disabled */
785 * Miscellaneous configurable options
787 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
790 * For booting Linux, the board info and command line data
791 * have to be in the first 64 MB of memory, since this is
792 * the maximum mapped by the Linux kernel during initialization.
794 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
795 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
797 #if defined(CONFIG_CMD_KGDB)
798 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
802 * Environment Configuration
804 #define CONFIG_HOSTNAME "unknown"
805 #define CONFIG_ROOTPATH "/opt/nfsroot"
806 #define CONFIG_BOOTFILE "uImage"
807 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
809 /* default location for tftp and bootm */
810 #define CONFIG_LOADADDR 1000000
813 #define __NOR_RST_CMD \
814 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
815 i2c mw 18 3 __SW_BOOT_MASK 1; reset
818 #define __SPI_RST_CMD \
819 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
820 i2c mw 18 3 __SW_BOOT_MASK 1; reset
823 #define __SD_RST_CMD \
824 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
825 i2c mw 18 3 __SW_BOOT_MASK 1; reset
827 #ifdef __SW_BOOT_NAND
828 #define __NAND_RST_CMD \
829 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
830 i2c mw 18 3 __SW_BOOT_MASK 1; reset
832 #ifdef __SW_BOOT_PCIE
833 #define __PCIE_RST_CMD \
834 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
835 i2c mw 18 3 __SW_BOOT_MASK 1; reset
838 #define CONFIG_EXTRA_ENV_SETTINGS \
840 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
841 "loadaddr=1000000\0" \
842 "bootfile=uImage\0" \
843 "tftpflash=tftpboot $loadaddr $uboot; " \
844 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
845 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
846 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
847 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
848 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
849 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
850 "consoledev=ttyS0\0" \
851 "ramdiskaddr=2000000\0" \
852 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
853 "fdtaddr=1e00000\0" \
855 "jffs2nor=mtdblock3\0" \
856 "norbootaddr=ef080000\0" \
857 "norfdtaddr=ef040000\0" \
858 "jffs2nand=mtdblock9\0" \
859 "nandbootaddr=100000\0" \
860 "nandfdtaddr=80000\0" \
861 "ramdisk_size=120000\0" \
862 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
863 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
864 __stringify(__NOR_RST_CMD)"\0" \
865 __stringify(__SPI_RST_CMD)"\0" \
866 __stringify(__SD_RST_CMD)"\0" \
867 __stringify(__NAND_RST_CMD)"\0" \
868 __stringify(__PCIE_RST_CMD)"\0"
870 #define CONFIG_NFSBOOTCOMMAND \
871 "setenv bootargs root=/dev/nfs rw " \
872 "nfsroot=$serverip:$rootpath " \
873 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
874 "console=$consoledev,$baudrate $othbootargs;" \
875 "tftp $loadaddr $bootfile;" \
876 "tftp $fdtaddr $fdtfile;" \
877 "bootm $loadaddr - $fdtaddr"
879 #define CONFIG_HDBOOT \
880 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
881 "console=$consoledev,$baudrate $othbootargs;" \
883 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
884 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
885 "bootm $loadaddr - $fdtaddr"
887 #define CONFIG_USB_FAT_BOOT \
888 "setenv bootargs root=/dev/ram rw " \
889 "console=$consoledev,$baudrate $othbootargs " \
890 "ramdisk_size=$ramdisk_size;" \
892 "fatload usb 0:2 $loadaddr $bootfile;" \
893 "fatload usb 0:2 $fdtaddr $fdtfile;" \
894 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
895 "bootm $loadaddr $ramdiskaddr $fdtaddr"
897 #define CONFIG_USB_EXT2_BOOT \
898 "setenv bootargs root=/dev/ram rw " \
899 "console=$consoledev,$baudrate $othbootargs " \
900 "ramdisk_size=$ramdisk_size;" \
902 "ext2load usb 0:4 $loadaddr $bootfile;" \
903 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
904 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
905 "bootm $loadaddr $ramdiskaddr $fdtaddr"
907 #define CONFIG_NORBOOT \
908 "setenv bootargs root=/dev/$jffs2nor rw " \
909 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
910 "bootm $norbootaddr - $norfdtaddr"
912 #define CONFIG_RAMBOOTCOMMAND \
913 "setenv bootargs root=/dev/ram rw " \
914 "console=$consoledev,$baudrate $othbootargs " \
915 "ramdisk_size=$ramdisk_size;" \
916 "tftp $ramdiskaddr $ramdiskfile;" \
917 "tftp $loadaddr $bootfile;" \
918 "tftp $fdtaddr $fdtfile;" \
919 "bootm $loadaddr $ramdiskaddr $fdtaddr"
921 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
923 #endif /* __CONFIG_H */