2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #define CONFIG_DISPLAY_BOARDINFO
15 #if defined(CONFIG_P1020MBG)
16 #define CONFIG_BOARDNAME "P1020MBG-PC"
18 #define CONFIG_VSC7385_ENET
20 #define __SW_BOOT_MASK 0x03
21 #define __SW_BOOT_NOR 0xe4
22 #define __SW_BOOT_SD 0x54
23 #define CONFIG_SYS_L2_SIZE (256 << 10)
26 #if defined(CONFIG_P1020UTM)
27 #define CONFIG_BOARDNAME "P1020UTM-PC"
29 #define __SW_BOOT_MASK 0x03
30 #define __SW_BOOT_NOR 0xe0
31 #define __SW_BOOT_SD 0x50
32 #define CONFIG_SYS_L2_SIZE (256 << 10)
35 #if defined(CONFIG_P1020RDB_PC)
36 #define CONFIG_BOARDNAME "P1020RDB-PC"
37 #define CONFIG_NAND_FSL_ELBC
39 #define CONFIG_VSC7385_ENET
41 #define __SW_BOOT_MASK 0x03
42 #define __SW_BOOT_NOR 0x5c
43 #define __SW_BOOT_SPI 0x1c
44 #define __SW_BOOT_SD 0x9c
45 #define __SW_BOOT_NAND 0xec
46 #define __SW_BOOT_PCIE 0x6c
47 #define CONFIG_SYS_L2_SIZE (256 << 10)
51 * P1020RDB-PD board has user selectable switches for evaluating different
52 * frequency and boot options for the P1020 device. The table that
53 * follow describe the available options. The front six binary number was in
54 * accordance with SW3[1:6].
55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
63 #if defined(CONFIG_P1020RDB_PD)
64 #define CONFIG_BOARDNAME "P1020RDB-PD"
65 #define CONFIG_NAND_FSL_ELBC
67 #define CONFIG_VSC7385_ENET
69 #define __SW_BOOT_MASK 0x03
70 #define __SW_BOOT_NOR 0x64
71 #define __SW_BOOT_SPI 0x34
72 #define __SW_BOOT_SD 0x24
73 #define __SW_BOOT_NAND 0x44
74 #define __SW_BOOT_PCIE 0x74
75 #define CONFIG_SYS_L2_SIZE (256 << 10)
77 * Dynamic MTD Partition support with mtdparts
79 #define CONFIG_MTD_DEVICE
80 #define CONFIG_MTD_PARTITIONS
81 #define CONFIG_CMD_MTDPARTS
82 #define CONFIG_FLASH_CFI_MTD
83 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
88 #if defined(CONFIG_P1021RDB)
89 #define CONFIG_BOARDNAME "P1021RDB-PC"
90 #define CONFIG_NAND_FSL_ELBC
93 #define CONFIG_VSC7385_ENET
94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
95 addresses in the LBC */
96 #define __SW_BOOT_MASK 0x03
97 #define __SW_BOOT_NOR 0x5c
98 #define __SW_BOOT_SPI 0x1c
99 #define __SW_BOOT_SD 0x9c
100 #define __SW_BOOT_NAND 0xec
101 #define __SW_BOOT_PCIE 0x6c
102 #define CONFIG_SYS_L2_SIZE (256 << 10)
104 * Dynamic MTD Partition support with mtdparts
106 #define CONFIG_MTD_DEVICE
107 #define CONFIG_MTD_PARTITIONS
108 #define CONFIG_CMD_MTDPARTS
109 #define CONFIG_FLASH_CFI_MTD
110 #ifdef CONFIG_PHYS_64BIT
111 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
113 "256k(dtb),4608k(kernel),9728k(fs)," \
114 "256k(qe-ucode-firmware),1280k(u-boot)"
116 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
118 "256k(dtb),4608k(kernel),9728k(fs)," \
119 "256k(qe-ucode-firmware),1280k(u-boot)"
123 #if defined(CONFIG_P1024RDB)
124 #define CONFIG_BOARDNAME "P1024RDB"
125 #define CONFIG_NAND_FSL_ELBC
128 #define __SW_BOOT_MASK 0xf3
129 #define __SW_BOOT_NOR 0x00
130 #define __SW_BOOT_SPI 0x08
131 #define __SW_BOOT_SD 0x04
132 #define __SW_BOOT_NAND 0x0c
133 #define CONFIG_SYS_L2_SIZE (256 << 10)
136 #if defined(CONFIG_P1025RDB)
137 #define CONFIG_BOARDNAME "P1025RDB"
138 #define CONFIG_NAND_FSL_ELBC
143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
144 addresses in the LBC */
145 #define __SW_BOOT_MASK 0xf3
146 #define __SW_BOOT_NOR 0x00
147 #define __SW_BOOT_SPI 0x08
148 #define __SW_BOOT_SD 0x04
149 #define __SW_BOOT_NAND 0x0c
150 #define CONFIG_SYS_L2_SIZE (256 << 10)
153 #if defined(CONFIG_P2020RDB)
154 #define CONFIG_BOARDNAME "P2020RDB-PCA"
155 #define CONFIG_NAND_FSL_ELBC
157 #define CONFIG_VSC7385_ENET
158 #define __SW_BOOT_MASK 0x03
159 #define __SW_BOOT_NOR 0xc8
160 #define __SW_BOOT_SPI 0x28
161 #define __SW_BOOT_SD 0x68 /* or 0x18 */
162 #define __SW_BOOT_NAND 0xe8
163 #define __SW_BOOT_PCIE 0xa8
164 #define CONFIG_SYS_L2_SIZE (512 << 10)
166 * Dynamic MTD Partition support with mtdparts
168 #define CONFIG_MTD_DEVICE
169 #define CONFIG_MTD_PARTITIONS
170 #define CONFIG_CMD_MTDPARTS
171 #define CONFIG_FLASH_CFI_MTD
172 #ifdef CONFIG_PHYS_64BIT
173 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
177 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
184 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
185 #define CONFIG_SPL_SERIAL_SUPPORT
186 #define CONFIG_SPL_MMC_SUPPORT
187 #define CONFIG_SPL_MMC_MINIMAL
188 #define CONFIG_SPL_FLUSH_IMAGE
189 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
190 #define CONFIG_SPL_LIBGENERIC_SUPPORT
191 #define CONFIG_SPL_LIBCOMMON_SUPPORT
192 #define CONFIG_SPL_I2C_SUPPORT
193 #define CONFIG_FSL_LAW /* Use common FSL init code */
194 #define CONFIG_SYS_TEXT_BASE 0x11001000
195 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
196 #define CONFIG_SPL_PAD_TO 0x20000
197 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
198 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
199 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
200 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
201 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
202 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
203 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
204 #define CONFIG_SPL_MMC_BOOT
205 #ifdef CONFIG_SPL_BUILD
206 #define CONFIG_SPL_COMMON_INIT_DDR
210 #ifdef CONFIG_SPIFLASH
211 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
212 #define CONFIG_SPL_SERIAL_SUPPORT
213 #define CONFIG_SPL_SPI_SUPPORT
214 #define CONFIG_SPL_SPI_FLASH_SUPPORT
215 #define CONFIG_SPL_SPI_FLASH_MINIMAL
216 #define CONFIG_SPL_FLUSH_IMAGE
217 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
218 #define CONFIG_SPL_LIBGENERIC_SUPPORT
219 #define CONFIG_SPL_LIBCOMMON_SUPPORT
220 #define CONFIG_SPL_I2C_SUPPORT
221 #define CONFIG_FSL_LAW /* Use common FSL init code */
222 #define CONFIG_SYS_TEXT_BASE 0x11001000
223 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
224 #define CONFIG_SPL_PAD_TO 0x20000
225 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
226 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
227 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
228 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
229 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
230 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
231 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
232 #define CONFIG_SPL_SPI_BOOT
233 #ifdef CONFIG_SPL_BUILD
234 #define CONFIG_SPL_COMMON_INIT_DDR
239 #ifdef CONFIG_TPL_BUILD
240 #define CONFIG_SPL_NAND_BOOT
241 #define CONFIG_SPL_FLUSH_IMAGE
242 #define CONFIG_SPL_NAND_INIT
243 #define CONFIG_TPL_SERIAL_SUPPORT
244 #define CONFIG_TPL_LIBGENERIC_SUPPORT
245 #define CONFIG_TPL_LIBCOMMON_SUPPORT
246 #define CONFIG_TPL_I2C_SUPPORT
247 #define CONFIG_TPL_NAND_SUPPORT
248 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT
249 #define CONFIG_SPL_COMMON_INIT_DDR
250 #define CONFIG_SPL_MAX_SIZE (128 << 10)
251 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
252 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
253 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
254 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
255 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
256 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
257 #elif defined(CONFIG_SPL_BUILD)
258 #define CONFIG_SPL_INIT_MINIMAL
259 #define CONFIG_SPL_SERIAL_SUPPORT
260 #define CONFIG_SPL_NAND_SUPPORT
261 #define CONFIG_SPL_FLUSH_IMAGE
262 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
263 #define CONFIG_SPL_TEXT_BASE 0xff800000
264 #define CONFIG_SPL_MAX_SIZE 4096
265 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
266 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
267 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
268 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
269 #endif /* not CONFIG_TPL_BUILD */
271 #define CONFIG_SPL_PAD_TO 0x20000
272 #define CONFIG_TPL_PAD_TO 0x20000
273 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
274 #define CONFIG_SYS_TEXT_BASE 0x11001000
275 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
278 #ifndef CONFIG_SYS_TEXT_BASE
279 #define CONFIG_SYS_TEXT_BASE 0xeff40000
282 #ifndef CONFIG_RESET_VECTOR_ADDRESS
283 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
286 #ifndef CONFIG_SYS_MONITOR_BASE
287 #ifdef CONFIG_SPL_BUILD
288 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
290 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
294 /* High Level Configuration Options */
300 #define CONFIG_FSL_ELBC
302 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
303 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
304 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
305 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
306 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
307 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
309 #define CONFIG_FSL_LAW
310 #define CONFIG_TSEC_ENET /* tsec ethernet support */
311 #define CONFIG_ENV_OVERWRITE
313 #define CONFIG_CMD_SATA
314 #define CONFIG_SATA_SIL
315 #define CONFIG_SYS_SATA_MAX_DEVICE 2
316 #define CONFIG_LIBATA
319 #if defined(CONFIG_P2020RDB)
320 #define CONFIG_SYS_CLK_FREQ 100000000
322 #define CONFIG_SYS_CLK_FREQ 66666666
324 #define CONFIG_DDR_CLK_FREQ 66666666
326 #define CONFIG_HWCONFIG
328 * These can be toggled for performance analysis, otherwise use default.
330 #define CONFIG_L2_CACHE
333 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
335 #define CONFIG_ENABLE_36BIT_PHYS
337 #ifdef CONFIG_PHYS_64BIT
338 #define CONFIG_ADDR_MAP 1
339 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
342 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
343 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
344 #define CONFIG_PANIC_HANG /* do not reset board on panic */
346 #define CONFIG_SYS_CCSRBAR 0xffe00000
347 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
349 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
351 #ifdef CONFIG_SPL_BUILD
352 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
356 #define CONFIG_SYS_FSL_DDR3
357 #define CONFIG_SYS_DDR_RAW_TIMING
358 #define CONFIG_DDR_SPD
359 #define CONFIG_SYS_SPD_BUS_NUM 1
360 #define SPD_EEPROM_ADDRESS 0x52
361 #undef CONFIG_FSL_DDR_INTERACTIVE
363 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
364 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
365 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
367 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
368 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
370 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
371 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
372 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
374 #define CONFIG_NUM_DDR_CONTROLLERS 1
375 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
377 /* Default settings for DDR3 */
378 #ifndef CONFIG_P2020RDB
379 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
380 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
381 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
382 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
383 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
384 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
386 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
387 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
388 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
389 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
391 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
392 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
393 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
394 #define CONFIG_SYS_DDR_RCW_1 0x00000000
395 #define CONFIG_SYS_DDR_RCW_2 0x00000000
396 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
397 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
398 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
399 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
401 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
402 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
403 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
404 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
405 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
406 #define CONFIG_SYS_DDR_MODE_1 0x40461520
407 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
408 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
411 #undef CONFIG_CLOCKS_IN_MHZ
416 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
417 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
418 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
419 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
421 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
422 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
423 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
424 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
425 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
426 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
427 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
431 * Local Bus Definitions
433 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
434 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
435 #define CONFIG_SYS_FLASH_BASE 0xec000000
436 #elif defined(CONFIG_P1020UTM)
437 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
438 #define CONFIG_SYS_FLASH_BASE 0xee000000
440 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
441 #define CONFIG_SYS_FLASH_BASE 0xef000000
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
447 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
450 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
453 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
455 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
456 #define CONFIG_SYS_FLASH_QUIET_TEST
457 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
459 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
461 #undef CONFIG_SYS_FLASH_CHECKSUM
462 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
463 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
465 #define CONFIG_FLASH_CFI_DRIVER
466 #define CONFIG_SYS_FLASH_CFI
467 #define CONFIG_SYS_FLASH_EMPTY_INFO
468 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
471 #ifdef CONFIG_NAND_FSL_ELBC
472 #define CONFIG_SYS_NAND_BASE 0xff800000
473 #ifdef CONFIG_PHYS_64BIT
474 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
476 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
479 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
480 #define CONFIG_SYS_MAX_NAND_DEVICE 1
481 #define CONFIG_CMD_NAND
482 #if defined(CONFIG_P1020RDB_PD)
483 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
485 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
488 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
489 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
490 | BR_PS_8 /* Port Size = 8 bit */ \
491 | BR_MS_FCM /* MSEL = FCM */ \
493 #if defined(CONFIG_P1020RDB_PD)
494 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
495 | OR_FCM_PGS /* Large Page*/ \
503 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
511 #endif /* CONFIG_NAND_FSL_ELBC */
513 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
515 #define CONFIG_SYS_INIT_RAM_LOCK
516 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
517 #ifdef CONFIG_PHYS_64BIT
518 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
519 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
520 /* The assembler doesn't like typecast */
521 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
522 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
523 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
525 /* Initial L1 address */
526 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
527 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
528 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
530 /* Size of used area in RAM */
531 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
533 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
534 GENERATED_GBL_DATA_SIZE)
535 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
537 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
538 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
540 #define CONFIG_SYS_CPLD_BASE 0xffa00000
541 #ifdef CONFIG_PHYS_64BIT
542 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
544 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
546 /* CPLD config size: 1Mb */
547 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
549 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
551 #define CONFIG_SYS_PMC_BASE 0xff980000
552 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
553 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
555 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
556 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
560 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
561 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
562 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
563 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
565 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
566 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
567 #ifdef CONFIG_NAND_FSL_ELBC
568 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
569 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
572 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
573 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
576 #ifdef CONFIG_VSC7385_ENET
577 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
579 #ifdef CONFIG_PHYS_64BIT
580 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
582 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
585 #define CONFIG_SYS_VSC7385_BR_PRELIM \
586 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
587 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
588 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
589 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
591 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
592 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
594 /* The size of the VSC7385 firmware image */
595 #define CONFIG_VSC7385_IMAGE_SIZE 8192
599 * Config the L2 Cache as L2 SRAM
601 #if defined(CONFIG_SPL_BUILD)
602 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
603 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
604 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
605 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
606 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
607 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
608 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
609 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
610 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
611 #if defined(CONFIG_P2020RDB)
612 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
614 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
616 #elif defined(CONFIG_NAND)
617 #ifdef CONFIG_TPL_BUILD
618 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
619 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
620 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
621 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
622 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
623 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
624 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
625 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
627 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
628 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
629 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
630 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
631 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
632 #endif /* CONFIG_TPL_BUILD */
636 /* Serial Port - controlled on board with jumper J8
640 #define CONFIG_CONS_INDEX 1
641 #undef CONFIG_SERIAL_SOFTWARE_FIFO
642 #define CONFIG_SYS_NS16550_SERIAL
643 #define CONFIG_SYS_NS16550_REG_SIZE 1
644 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
645 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
646 #define CONFIG_NS16550_MIN_FUNCTIONS
649 #define CONFIG_SYS_BAUDRATE_TABLE \
650 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
652 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
653 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
656 #define CONFIG_SYS_I2C
657 #define CONFIG_SYS_I2C_FSL
658 #define CONFIG_SYS_FSL_I2C_SPEED 400000
659 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
660 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
661 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
662 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
663 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
664 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
665 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
666 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
671 #undef CONFIG_ID_EEPROM
673 #define CONFIG_RTC_PT7C4338
674 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
675 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
677 /* enable read and write access to EEPROM */
678 #define CONFIG_CMD_EEPROM
679 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
680 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
681 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
684 * eSPI - Enhanced SPI
686 #define CONFIG_HARD_SPI
688 #if defined(CONFIG_SPI_FLASH)
689 #define CONFIG_SF_DEFAULT_SPEED 10000000
690 #define CONFIG_SF_DEFAULT_MODE 0
693 #if defined(CONFIG_PCI)
696 * Memory space is mapped 1-1, but I/O space must start from 0.
699 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
700 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
701 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
702 #ifdef CONFIG_PHYS_64BIT
703 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
704 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
706 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
707 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
709 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
710 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
711 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
712 #ifdef CONFIG_PHYS_64BIT
713 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
715 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
717 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
719 /* controller 1, Slot 2, tgtid 1, Base address a000 */
720 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
721 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
722 #ifdef CONFIG_PHYS_64BIT
723 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
724 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
726 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
727 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
729 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
730 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
731 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
732 #ifdef CONFIG_PHYS_64BIT
733 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
735 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
737 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
739 #define CONFIG_PCI_PNP /* do pci plug-and-play */
740 #define CONFIG_CMD_PCI
742 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
743 #define CONFIG_DOS_PARTITION
744 #endif /* CONFIG_PCI */
746 #if defined(CONFIG_TSEC_ENET)
747 #define CONFIG_MII /* MII PHY management */
749 #define CONFIG_TSEC1_NAME "eTSEC1"
751 #define CONFIG_TSEC2_NAME "eTSEC2"
753 #define CONFIG_TSEC3_NAME "eTSEC3"
755 #define TSEC1_PHY_ADDR 2
756 #define TSEC2_PHY_ADDR 0
757 #define TSEC3_PHY_ADDR 1
759 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
760 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
761 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
763 #define TSEC1_PHYIDX 0
764 #define TSEC2_PHYIDX 0
765 #define TSEC3_PHYIDX 0
767 #define CONFIG_ETHPRIME "eTSEC1"
769 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
771 #define CONFIG_HAS_ETH0
772 #define CONFIG_HAS_ETH1
773 #define CONFIG_HAS_ETH2
774 #endif /* CONFIG_TSEC_ENET */
777 /* QE microcode/firmware address */
778 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
779 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
780 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
781 #endif /* CONFIG_QE */
783 #ifdef CONFIG_P1025RDB
785 * QE UEC ethernet configuration
787 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
789 #undef CONFIG_UEC_ETH
790 #define CONFIG_PHY_MODE_NEED_CHANGE
792 #define CONFIG_UEC_ETH1 /* ETH1 */
793 #define CONFIG_HAS_ETH0
795 #ifdef CONFIG_UEC_ETH1
796 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
797 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
798 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
799 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
800 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
801 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
802 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
803 #endif /* CONFIG_UEC_ETH1 */
805 #define CONFIG_UEC_ETH5 /* ETH5 */
806 #define CONFIG_HAS_ETH1
808 #ifdef CONFIG_UEC_ETH5
809 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
810 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
811 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
812 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
813 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
814 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
815 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
816 #endif /* CONFIG_UEC_ETH5 */
817 #endif /* CONFIG_P1025RDB */
822 #ifdef CONFIG_SPIFLASH
823 #define CONFIG_ENV_IS_IN_SPI_FLASH
824 #define CONFIG_ENV_SPI_BUS 0
825 #define CONFIG_ENV_SPI_CS 0
826 #define CONFIG_ENV_SPI_MAX_HZ 10000000
827 #define CONFIG_ENV_SPI_MODE 0
828 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
829 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
830 #define CONFIG_ENV_SECT_SIZE 0x10000
831 #elif defined(CONFIG_SDCARD)
832 #define CONFIG_ENV_IS_IN_MMC
833 #define CONFIG_FSL_FIXED_MMC_LOCATION
834 #define CONFIG_ENV_SIZE 0x2000
835 #define CONFIG_SYS_MMC_ENV_DEV 0
836 #elif defined(CONFIG_NAND)
837 #ifdef CONFIG_TPL_BUILD
838 #define CONFIG_ENV_SIZE 0x2000
839 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
841 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
843 #define CONFIG_ENV_IS_IN_NAND
844 #define CONFIG_ENV_OFFSET (1024 * 1024)
845 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
846 #elif defined(CONFIG_SYS_RAMBOOT)
847 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
848 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
849 #define CONFIG_ENV_SIZE 0x2000
851 #define CONFIG_ENV_IS_IN_FLASH
852 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
853 #define CONFIG_ENV_SIZE 0x2000
854 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
857 #define CONFIG_LOADS_ECHO /* echo on for serial download */
858 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
861 * Command line configuration.
863 #define CONFIG_CMD_IRQ
864 #define CONFIG_CMD_DATE
865 #define CONFIG_CMD_REGINFO
870 #define CONFIG_HAS_FSL_DR_USB
872 #if defined(CONFIG_HAS_FSL_DR_USB)
873 #define CONFIG_USB_EHCI
875 #ifdef CONFIG_USB_EHCI
876 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
877 #define CONFIG_USB_EHCI_FSL
881 #if defined(CONFIG_P1020RDB_PD)
882 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
888 #define CONFIG_FSL_ESDHC
889 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
890 #define CONFIG_GENERIC_MMC
893 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
894 || defined(CONFIG_FSL_SATA)
895 #define CONFIG_DOS_PARTITION
898 #undef CONFIG_WATCHDOG /* watchdog disabled */
901 * Miscellaneous configurable options
903 #define CONFIG_SYS_LONGHELP /* undef to save memory */
904 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
905 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
906 #if defined(CONFIG_CMD_KGDB)
907 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
909 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
911 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
912 /* Print Buffer Size */
913 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
914 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
917 * For booting Linux, the board info and command line data
918 * have to be in the first 64 MB of memory, since this is
919 * the maximum mapped by the Linux kernel during initialization.
921 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
922 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
924 #if defined(CONFIG_CMD_KGDB)
925 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
929 * Environment Configuration
931 #define CONFIG_HOSTNAME unknown
932 #define CONFIG_ROOTPATH "/opt/nfsroot"
933 #define CONFIG_BOOTFILE "uImage"
934 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
936 /* default location for tftp and bootm */
937 #define CONFIG_LOADADDR 1000000
939 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
941 #define CONFIG_BAUDRATE 115200
944 #define __NOR_RST_CMD \
945 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
946 i2c mw 18 3 __SW_BOOT_MASK 1; reset
949 #define __SPI_RST_CMD \
950 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
951 i2c mw 18 3 __SW_BOOT_MASK 1; reset
954 #define __SD_RST_CMD \
955 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
956 i2c mw 18 3 __SW_BOOT_MASK 1; reset
958 #ifdef __SW_BOOT_NAND
959 #define __NAND_RST_CMD \
960 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
961 i2c mw 18 3 __SW_BOOT_MASK 1; reset
963 #ifdef __SW_BOOT_PCIE
964 #define __PCIE_RST_CMD \
965 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
966 i2c mw 18 3 __SW_BOOT_MASK 1; reset
969 #define CONFIG_EXTRA_ENV_SETTINGS \
971 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
972 "loadaddr=1000000\0" \
973 "bootfile=uImage\0" \
974 "tftpflash=tftpboot $loadaddr $uboot; " \
975 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
976 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
977 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
978 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
979 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
980 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
981 "consoledev=ttyS0\0" \
982 "ramdiskaddr=2000000\0" \
983 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
984 "fdtaddr=1e00000\0" \
986 "jffs2nor=mtdblock3\0" \
987 "norbootaddr=ef080000\0" \
988 "norfdtaddr=ef040000\0" \
989 "jffs2nand=mtdblock9\0" \
990 "nandbootaddr=100000\0" \
991 "nandfdtaddr=80000\0" \
992 "ramdisk_size=120000\0" \
993 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
994 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
995 __stringify(__NOR_RST_CMD)"\0" \
996 __stringify(__SPI_RST_CMD)"\0" \
997 __stringify(__SD_RST_CMD)"\0" \
998 __stringify(__NAND_RST_CMD)"\0" \
999 __stringify(__PCIE_RST_CMD)"\0"
1001 #define CONFIG_NFSBOOTCOMMAND \
1002 "setenv bootargs root=/dev/nfs rw " \
1003 "nfsroot=$serverip:$rootpath " \
1004 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
1005 "console=$consoledev,$baudrate $othbootargs;" \
1006 "tftp $loadaddr $bootfile;" \
1007 "tftp $fdtaddr $fdtfile;" \
1008 "bootm $loadaddr - $fdtaddr"
1010 #define CONFIG_HDBOOT \
1011 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
1012 "console=$consoledev,$baudrate $othbootargs;" \
1014 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
1015 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
1016 "bootm $loadaddr - $fdtaddr"
1018 #define CONFIG_USB_FAT_BOOT \
1019 "setenv bootargs root=/dev/ram rw " \
1020 "console=$consoledev,$baudrate $othbootargs " \
1021 "ramdisk_size=$ramdisk_size;" \
1023 "fatload usb 0:2 $loadaddr $bootfile;" \
1024 "fatload usb 0:2 $fdtaddr $fdtfile;" \
1025 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
1026 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1028 #define CONFIG_USB_EXT2_BOOT \
1029 "setenv bootargs root=/dev/ram rw " \
1030 "console=$consoledev,$baudrate $othbootargs " \
1031 "ramdisk_size=$ramdisk_size;" \
1033 "ext2load usb 0:4 $loadaddr $bootfile;" \
1034 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1035 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1036 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1038 #define CONFIG_NORBOOT \
1039 "setenv bootargs root=/dev/$jffs2nor rw " \
1040 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
1041 "bootm $norbootaddr - $norfdtaddr"
1043 #define CONFIG_RAMBOOTCOMMAND \
1044 "setenv bootargs root=/dev/ram rw " \
1045 "console=$consoledev,$baudrate $othbootargs " \
1046 "ramdisk_size=$ramdisk_size;" \
1047 "tftp $ramdiskaddr $ramdiskfile;" \
1048 "tftp $loadaddr $bootfile;" \
1049 "tftp $fdtaddr $fdtfile;" \
1050 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1052 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
1054 #endif /* __CONFIG_H */