2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
14 #define CONFIG_PHYS_64BIT
17 #if defined(CONFIG_P1020MBG)
18 #define CONFIG_BOARDNAME "P1020MBG-PC"
20 #define CONFIG_VSC7385_ENET
22 #define __SW_BOOT_MASK 0x03
23 #define __SW_BOOT_NOR 0xe4
24 #define __SW_BOOT_SD 0x54
25 #define CONFIG_SYS_L2_SIZE (256 << 10)
28 #if defined(CONFIG_P1020UTM)
29 #define CONFIG_BOARDNAME "P1020UTM-PC"
31 #define __SW_BOOT_MASK 0x03
32 #define __SW_BOOT_NOR 0xe0
33 #define __SW_BOOT_SD 0x50
34 #define CONFIG_SYS_L2_SIZE (256 << 10)
37 #if defined(CONFIG_P1020RDB_PC)
38 #define CONFIG_BOARDNAME "P1020RDB-PC"
39 #define CONFIG_NAND_FSL_ELBC
41 #define CONFIG_SPI_FLASH
42 #define CONFIG_VSC7385_ENET
44 #define __SW_BOOT_MASK 0x03
45 #define __SW_BOOT_NOR 0x5c
46 #define __SW_BOOT_SPI 0x1c
47 #define __SW_BOOT_SD 0x9c
48 #define __SW_BOOT_NAND 0xec
49 #define __SW_BOOT_PCIE 0x6c
50 #define CONFIG_SYS_L2_SIZE (256 << 10)
54 * P1020RDB-PD board has user selectable switches for evaluating different
55 * frequency and boot options for the P1020 device. The table that
56 * follow describe the available options. The front six binary number was in
57 * accordance with SW3[1:6].
58 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
59 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
60 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
61 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
62 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
63 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
64 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
66 #if defined(CONFIG_P1020RDB_PD)
67 #define CONFIG_BOARDNAME "P1020RDB-PD"
68 #define CONFIG_NAND_FSL_ELBC
70 #define CONFIG_SPI_FLASH
71 #define CONFIG_VSC7385_ENET
73 #define __SW_BOOT_MASK 0x03
74 #define __SW_BOOT_NOR 0x64
75 #define __SW_BOOT_SPI 0x34
76 #define __SW_BOOT_SD 0x24
77 #define __SW_BOOT_NAND 0x44
78 #define __SW_BOOT_PCIE 0x74
79 #define CONFIG_SYS_L2_SIZE (256 << 10)
82 #if defined(CONFIG_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
87 #define CONFIG_SPI_FLASH
88 #define CONFIG_VSC7385_ENET
89 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
90 addresses in the LBC */
91 #define __SW_BOOT_MASK 0x03
92 #define __SW_BOOT_NOR 0x5c
93 #define __SW_BOOT_SPI 0x1c
94 #define __SW_BOOT_SD 0x9c
95 #define __SW_BOOT_NAND 0xec
96 #define __SW_BOOT_PCIE 0x6c
97 #define CONFIG_SYS_L2_SIZE (256 << 10)
100 #if defined(CONFIG_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
105 #define CONFIG_SPI_FLASH
106 #define __SW_BOOT_MASK 0xf3
107 #define __SW_BOOT_NOR 0x00
108 #define __SW_BOOT_SPI 0x08
109 #define __SW_BOOT_SD 0x04
110 #define __SW_BOOT_NAND 0x0c
111 #define CONFIG_SYS_L2_SIZE (256 << 10)
114 #if defined(CONFIG_P1025RDB)
115 #define CONFIG_BOARDNAME "P1025RDB"
116 #define CONFIG_NAND_FSL_ELBC
120 #define CONFIG_SPI_FLASH
122 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
123 addresses in the LBC */
124 #define __SW_BOOT_MASK 0xf3
125 #define __SW_BOOT_NOR 0x00
126 #define __SW_BOOT_SPI 0x08
127 #define __SW_BOOT_SD 0x04
128 #define __SW_BOOT_NAND 0x0c
129 #define CONFIG_SYS_L2_SIZE (256 << 10)
132 #if defined(CONFIG_P2020RDB)
133 #define CONFIG_BOARDNAME "P2020RDB-PCA"
134 #define CONFIG_NAND_FSL_ELBC
136 #define CONFIG_SPI_FLASH
137 #define CONFIG_VSC7385_ENET
138 #define __SW_BOOT_MASK 0x03
139 #define __SW_BOOT_NOR 0xc8
140 #define __SW_BOOT_SPI 0x28
141 #define __SW_BOOT_SD 0x68 /* or 0x18 */
142 #define __SW_BOOT_NAND 0xe8
143 #define __SW_BOOT_PCIE 0xa8
144 #define CONFIG_SYS_L2_SIZE (512 << 10)
147 #if CONFIG_SYS_L2_SIZE >= (512 << 10)
149 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
150 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
151 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
155 #define CONFIG_RAMBOOT_SDCARD
156 #define CONFIG_SYS_RAMBOOT
157 #define CONFIG_SYS_EXTRA_ENV_RELOC
158 #define CONFIG_SYS_TEXT_BASE 0x11000000
159 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
162 #ifdef CONFIG_SPIFLASH
163 #define CONFIG_RAMBOOT_SPIFLASH
164 #define CONFIG_SYS_RAMBOOT
165 #define CONFIG_SYS_EXTRA_ENV_RELOC
166 #define CONFIG_SYS_TEXT_BASE 0x11000000
167 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
172 #define CONFIG_SPL_INIT_MINIMAL
173 #define CONFIG_SPL_SERIAL_SUPPORT
174 #define CONFIG_SPL_NAND_SUPPORT
175 #define CONFIG_SPL_FLUSH_IMAGE
176 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
178 #define CONFIG_SPL_TEXT_BASE 0xfffff000
179 #define CONFIG_SPL_MAX_SIZE 4096
181 #ifdef CONFIG_SYS_INIT_L2_ADDR
182 /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
183 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
184 #define CONFIG_SPL_RELOC_TEXT_BASE \
185 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
186 #define CONFIG_SPL_RELOC_STACK \
187 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
188 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
189 #define CONFIG_SYS_NAND_U_BOOT_START \
190 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
192 #define CONFIG_SYS_TEXT_BASE 0x00201000
193 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
194 #define CONFIG_SPL_RELOC_STACK 0x00100000
195 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
196 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
199 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
200 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
201 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
204 #ifndef CONFIG_SYS_TEXT_BASE
205 #define CONFIG_SYS_TEXT_BASE 0xeff80000
208 #ifndef CONFIG_RESET_VECTOR_ADDRESS
209 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
212 #ifndef CONFIG_SYS_MONITOR_BASE
213 #ifdef CONFIG_SPL_BUILD
214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
220 /* High Level Configuration Options */
223 #define CONFIG_MPC85xx
227 #define CONFIG_FSL_ELBC
229 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
230 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
231 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
232 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
233 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
234 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
236 #define CONFIG_FSL_LAW
237 #define CONFIG_TSEC_ENET /* tsec ethernet support */
238 #define CONFIG_ENV_OVERWRITE
240 #define CONFIG_CMD_SATA
241 #define CONFIG_SATA_SIL
242 #define CONFIG_SYS_SATA_MAX_DEVICE 2
243 #define CONFIG_LIBATA
246 #if defined(CONFIG_P2020RDB)
247 #define CONFIG_SYS_CLK_FREQ 100000000
249 #define CONFIG_SYS_CLK_FREQ 66666666
251 #define CONFIG_DDR_CLK_FREQ 66666666
253 #define CONFIG_HWCONFIG
255 * These can be toggled for performance analysis, otherwise use default.
257 #define CONFIG_L2_CACHE
260 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
262 #define CONFIG_ENABLE_36BIT_PHYS
264 #ifdef CONFIG_PHYS_64BIT
265 #define CONFIG_ADDR_MAP 1
266 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
269 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
270 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
271 #define CONFIG_PANIC_HANG /* do not reset board on panic */
273 #define CONFIG_SYS_CCSRBAR 0xffe00000
274 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
276 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
278 #ifdef CONFIG_SPL_BUILD
279 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
283 #define CONFIG_FSL_DDR3
284 #define CONFIG_SYS_DDR_RAW_TIMING
285 #define CONFIG_DDR_SPD
286 #define CONFIG_SYS_SPD_BUS_NUM 1
287 #define SPD_EEPROM_ADDRESS 0x52
288 #undef CONFIG_FSL_DDR_INTERACTIVE
290 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
291 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
292 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
294 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
295 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
297 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
298 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
299 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
301 #define CONFIG_NUM_DDR_CONTROLLERS 1
302 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
304 /* Default settings for DDR3 */
305 #ifndef CONFIG_P2020RDB
306 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
307 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
308 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
309 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
310 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
311 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
313 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
314 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
315 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
316 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
318 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
319 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
320 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
321 #define CONFIG_SYS_DDR_RCW_1 0x00000000
322 #define CONFIG_SYS_DDR_RCW_2 0x00000000
323 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
324 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
325 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
326 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
328 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
329 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
330 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
331 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
332 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
333 #define CONFIG_SYS_DDR_MODE_1 0x40461520
334 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
335 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
338 #undef CONFIG_CLOCKS_IN_MHZ
343 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
344 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
345 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
346 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
348 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
349 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
350 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
351 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
352 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
353 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
354 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
359 * Local Bus Definitions
361 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
362 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
363 #define CONFIG_SYS_FLASH_BASE 0xec000000
364 #elif defined(CONFIG_P1020UTM)
365 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
366 #define CONFIG_SYS_FLASH_BASE 0xee000000
368 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
369 #define CONFIG_SYS_FLASH_BASE 0xef000000
373 #ifdef CONFIG_PHYS_64BIT
374 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
376 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
379 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
382 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
384 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
385 #define CONFIG_SYS_FLASH_QUIET_TEST
386 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
388 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
390 #undef CONFIG_SYS_FLASH_CHECKSUM
391 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
392 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
394 #define CONFIG_FLASH_CFI_DRIVER
395 #define CONFIG_SYS_FLASH_CFI
396 #define CONFIG_SYS_FLASH_EMPTY_INFO
397 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
400 #ifdef CONFIG_NAND_FSL_ELBC
401 #define CONFIG_SYS_NAND_BASE 0xff800000
402 #ifdef CONFIG_PHYS_64BIT
403 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
405 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
408 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
409 #define CONFIG_SYS_MAX_NAND_DEVICE 1
410 #define CONFIG_MTD_NAND_VERIFY_WRITE
411 #define CONFIG_CMD_NAND
412 #if defined(CONFIG_P1020RDB_PD)
413 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
415 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
418 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
419 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
420 | BR_PS_8 /* Port Size = 8 bit */ \
421 | BR_MS_FCM /* MSEL = FCM */ \
423 #if defined(CONFIG_P1020RDB_PD)
424 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
425 | OR_FCM_PGS /* Large Page*/ \
433 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
441 #endif /* CONFIG_NAND_FSL_ELBC */
443 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
445 #define CONFIG_SYS_INIT_RAM_LOCK
446 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
450 /* The assembler doesn't like typecast */
451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
452 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
453 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
455 /* Initial L1 address */
456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
460 /* Size of used area in RAM */
461 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
463 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
464 GENERATED_GBL_DATA_SIZE)
465 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
467 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
468 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
470 #define CONFIG_SYS_CPLD_BASE 0xffa00000
471 #ifdef CONFIG_PHYS_64BIT
472 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
474 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
476 /* CPLD config size: 1Mb */
477 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
479 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
481 #define CONFIG_SYS_PMC_BASE 0xff980000
482 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
483 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
485 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
486 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
490 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
491 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
492 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
493 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
495 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
496 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
497 #ifdef CONFIG_NAND_FSL_ELBC
498 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
499 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
502 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
503 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
507 #ifdef CONFIG_VSC7385_ENET
508 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
510 #ifdef CONFIG_PHYS_64BIT
511 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
513 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
516 #define CONFIG_SYS_VSC7385_BR_PRELIM \
517 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
518 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
519 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
520 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
522 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
523 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
525 /* The size of the VSC7385 firmware image */
526 #define CONFIG_VSC7385_IMAGE_SIZE 8192
529 /* Serial Port - controlled on board with jumper J8
533 #define CONFIG_CONS_INDEX 1
534 #undef CONFIG_SERIAL_SOFTWARE_FIFO
535 #define CONFIG_SYS_NS16550
536 #define CONFIG_SYS_NS16550_SERIAL
537 #define CONFIG_SYS_NS16550_REG_SIZE 1
538 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
539 #ifdef CONFIG_SPL_BUILD
540 #define CONFIG_NS16550_MIN_FUNCTIONS
543 #define CONFIG_SYS_BAUDRATE_TABLE \
544 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
546 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
547 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
549 /* Use the HUSH parser */
550 #define CONFIG_SYS_HUSH_PARSER
553 * Pass open firmware flat tree
555 #define CONFIG_OF_LIBFDT
556 #define CONFIG_OF_BOARD_SETUP
557 #define CONFIG_OF_STDOUT_VIA_ALIAS
559 /* new uImage format support */
561 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
564 #define CONFIG_SYS_I2C
565 #define CONFIG_SYS_I2C_FSL
566 #define CONFIG_SYS_FSL_I2C_SPEED 400000
567 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
568 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
569 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
570 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
571 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
572 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
573 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
574 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
579 #undef CONFIG_ID_EEPROM
581 #define CONFIG_RTC_PT7C4338
582 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
583 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
585 /* enable read and write access to EEPROM */
586 #define CONFIG_CMD_EEPROM
587 #define CONFIG_SYS_I2C_MULTI_EEPROMS
588 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
589 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
590 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
593 * eSPI - Enhanced SPI
595 #define CONFIG_HARD_SPI
596 #define CONFIG_FSL_ESPI
598 #if defined(CONFIG_SPI_FLASH)
599 #define CONFIG_SPI_FLASH_SPANSION
600 #define CONFIG_CMD_SF
601 #define CONFIG_SF_DEFAULT_SPEED 10000000
602 #define CONFIG_SF_DEFAULT_MODE 0
605 #if defined(CONFIG_PCI)
608 * Memory space is mapped 1-1, but I/O space must start from 0.
611 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
612 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
613 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
614 #ifdef CONFIG_PHYS_64BIT
615 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
616 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
618 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
619 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
621 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
622 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
623 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
624 #ifdef CONFIG_PHYS_64BIT
625 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
627 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
629 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
631 /* controller 1, Slot 2, tgtid 1, Base address a000 */
632 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
633 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
634 #ifdef CONFIG_PHYS_64BIT
635 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
636 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
638 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
639 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
641 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
642 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
643 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
644 #ifdef CONFIG_PHYS_64BIT
645 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
647 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
649 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
651 #define CONFIG_PCI_PNP /* do pci plug-and-play */
652 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
653 #define CONFIG_CMD_PCI
654 #define CONFIG_CMD_NET
656 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
657 #define CONFIG_DOS_PARTITION
658 #endif /* CONFIG_PCI */
660 #if defined(CONFIG_TSEC_ENET)
661 #define CONFIG_MII /* MII PHY management */
663 #define CONFIG_TSEC1_NAME "eTSEC1"
665 #define CONFIG_TSEC2_NAME "eTSEC2"
667 #define CONFIG_TSEC3_NAME "eTSEC3"
669 #define TSEC1_PHY_ADDR 2
670 #define TSEC2_PHY_ADDR 0
671 #define TSEC3_PHY_ADDR 1
673 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
674 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
675 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
677 #define TSEC1_PHYIDX 0
678 #define TSEC2_PHYIDX 0
679 #define TSEC3_PHYIDX 0
681 #define CONFIG_ETHPRIME "eTSEC1"
683 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
685 #define CONFIG_HAS_ETH0
686 #define CONFIG_HAS_ETH1
687 #define CONFIG_HAS_ETH2
688 #endif /* CONFIG_TSEC_ENET */
691 /* QE microcode/firmware address */
692 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
693 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
694 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
695 #endif /* CONFIG_QE */
697 #ifdef CONFIG_P1025RDB
699 * QE UEC ethernet configuration
701 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
703 #undef CONFIG_UEC_ETH
704 #define CONFIG_PHY_MODE_NEED_CHANGE
706 #define CONFIG_UEC_ETH1 /* ETH1 */
707 #define CONFIG_HAS_ETH0
709 #ifdef CONFIG_UEC_ETH1
710 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
711 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
712 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
713 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
714 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
715 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
716 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
717 #endif /* CONFIG_UEC_ETH1 */
719 #define CONFIG_UEC_ETH5 /* ETH5 */
720 #define CONFIG_HAS_ETH1
722 #ifdef CONFIG_UEC_ETH5
723 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
724 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
725 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
726 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
727 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
728 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
729 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
730 #endif /* CONFIG_UEC_ETH5 */
731 #endif /* CONFIG_P1025RDB */
736 #ifdef CONFIG_RAMBOOT_SPIFLASH
737 #define CONFIG_ENV_IS_IN_SPI_FLASH
738 #define CONFIG_ENV_SPI_BUS 0
739 #define CONFIG_ENV_SPI_CS 0
740 #define CONFIG_ENV_SPI_MAX_HZ 10000000
741 #define CONFIG_ENV_SPI_MODE 0
742 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
743 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
744 #define CONFIG_ENV_SECT_SIZE 0x10000
745 #elif defined(CONFIG_RAMBOOT_SDCARD)
746 #define CONFIG_ENV_IS_IN_MMC
747 #define CONFIG_FSL_FIXED_MMC_LOCATION
748 #define CONFIG_ENV_SIZE 0x2000
749 #define CONFIG_SYS_MMC_ENV_DEV 0
750 #elif defined(CONFIG_NAND)
751 #define CONFIG_ENV_IS_IN_NAND
752 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
753 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
754 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
755 #elif defined(CONFIG_SYS_RAMBOOT)
756 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
757 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
758 #define CONFIG_ENV_SIZE 0x2000
760 #define CONFIG_ENV_IS_IN_FLASH
761 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
762 #define CONFIG_ENV_ADDR 0xfff80000
764 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
766 #define CONFIG_ENV_SIZE 0x2000
767 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
770 #define CONFIG_LOADS_ECHO /* echo on for serial download */
771 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
774 * Command line configuration.
776 #include <config_cmd_default.h>
778 #define CONFIG_CMD_IRQ
779 #define CONFIG_CMD_PING
780 #define CONFIG_CMD_I2C
781 #define CONFIG_CMD_MII
782 #define CONFIG_CMD_DATE
783 #define CONFIG_CMD_ELF
784 #define CONFIG_CMD_SETEXPR
785 #define CONFIG_CMD_REGINFO
790 #define CONFIG_HAS_FSL_DR_USB
792 #if defined(CONFIG_HAS_FSL_DR_USB)
793 #define CONFIG_USB_EHCI
795 #ifdef CONFIG_USB_EHCI
796 #define CONFIG_CMD_USB
797 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
798 #define CONFIG_USB_EHCI_FSL
799 #define CONFIG_USB_STORAGE
806 #define CONFIG_FSL_ESDHC
807 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
808 #define CONFIG_CMD_MMC
809 #define CONFIG_GENERIC_MMC
812 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
813 || defined(CONFIG_FSL_SATA)
814 #define CONFIG_CMD_EXT2
815 #define CONFIG_CMD_FAT
816 #define CONFIG_DOS_PARTITION
819 #undef CONFIG_WATCHDOG /* watchdog disabled */
822 * Miscellaneous configurable options
824 #define CONFIG_SYS_LONGHELP /* undef to save memory */
825 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
826 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
827 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
828 #if defined(CONFIG_CMD_KGDB)
829 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
831 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
833 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
834 /* Print Buffer Size */
835 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
836 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
837 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
840 * For booting Linux, the board info and command line data
841 * have to be in the first 64 MB of memory, since this is
842 * the maximum mapped by the Linux kernel during initialization.
844 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
845 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
847 #if defined(CONFIG_CMD_KGDB)
848 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
849 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
853 * Environment Configuration
855 #define CONFIG_HOSTNAME unknown
856 #define CONFIG_ROOTPATH "/opt/nfsroot"
857 #define CONFIG_BOOTFILE "uImage"
858 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
860 /* default location for tftp and bootm */
861 #define CONFIG_LOADADDR 1000000
863 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
864 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
866 #define CONFIG_BAUDRATE 115200
869 #define __NOR_RST_CMD \
870 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
871 i2c mw 18 3 __SW_BOOT_MASK 1; reset
874 #define __SPI_RST_CMD \
875 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
876 i2c mw 18 3 __SW_BOOT_MASK 1; reset
879 #define __SD_RST_CMD \
880 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
881 i2c mw 18 3 __SW_BOOT_MASK 1; reset
883 #ifdef __SW_BOOT_NAND
884 #define __NAND_RST_CMD \
885 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
886 i2c mw 18 3 __SW_BOOT_MASK 1; reset
888 #ifdef __SW_BOOT_PCIE
889 #define __PCIE_RST_CMD \
890 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
891 i2c mw 18 3 __SW_BOOT_MASK 1; reset
894 #define CONFIG_EXTRA_ENV_SETTINGS \
896 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
897 "loadaddr=1000000\0" \
898 "bootfile=uImage\0" \
899 "tftpflash=tftpboot $loadaddr $uboot; " \
900 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
901 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
902 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
903 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
904 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
905 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
906 "consoledev=ttyS0\0" \
907 "ramdiskaddr=2000000\0" \
908 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
911 "jffs2nor=mtdblock3\0" \
912 "norbootaddr=ef080000\0" \
913 "norfdtaddr=ef040000\0" \
914 "jffs2nand=mtdblock9\0" \
915 "nandbootaddr=100000\0" \
916 "nandfdtaddr=80000\0" \
917 "ramdisk_size=120000\0" \
918 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
919 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
920 __stringify(__NOR_RST_CMD)"\0" \
921 __stringify(__SPI_RST_CMD)"\0" \
922 __stringify(__SD_RST_CMD)"\0" \
923 __stringify(__NAND_RST_CMD)"\0" \
924 __stringify(__PCIE_RST_CMD)"\0"
926 #define CONFIG_NFSBOOTCOMMAND \
927 "setenv bootargs root=/dev/nfs rw " \
928 "nfsroot=$serverip:$rootpath " \
929 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
930 "console=$consoledev,$baudrate $othbootargs;" \
931 "tftp $loadaddr $bootfile;" \
932 "tftp $fdtaddr $fdtfile;" \
933 "bootm $loadaddr - $fdtaddr"
935 #define CONFIG_HDBOOT \
936 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
937 "console=$consoledev,$baudrate $othbootargs;" \
939 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
940 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
941 "bootm $loadaddr - $fdtaddr"
943 #define CONFIG_USB_FAT_BOOT \
944 "setenv bootargs root=/dev/ram rw " \
945 "console=$consoledev,$baudrate $othbootargs " \
946 "ramdisk_size=$ramdisk_size;" \
948 "fatload usb 0:2 $loadaddr $bootfile;" \
949 "fatload usb 0:2 $fdtaddr $fdtfile;" \
950 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
951 "bootm $loadaddr $ramdiskaddr $fdtaddr"
953 #define CONFIG_USB_EXT2_BOOT \
954 "setenv bootargs root=/dev/ram rw " \
955 "console=$consoledev,$baudrate $othbootargs " \
956 "ramdisk_size=$ramdisk_size;" \
958 "ext2load usb 0:4 $loadaddr $bootfile;" \
959 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
960 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
961 "bootm $loadaddr $ramdiskaddr $fdtaddr"
963 #define CONFIG_NORBOOT \
964 "setenv bootargs root=/dev/$jffs2nor rw " \
965 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
966 "bootm $norbootaddr - $norfdtaddr"
968 #define CONFIG_RAMBOOTCOMMAND \
969 "setenv bootargs root=/dev/ram rw " \
970 "console=$consoledev,$baudrate $othbootargs " \
971 "ramdisk_size=$ramdisk_size;" \
972 "tftp $ramdiskaddr $ramdiskfile;" \
973 "tftp $loadaddr $bootfile;" \
974 "tftp $fdtaddr $fdtfile;" \
975 "bootm $loadaddr $ramdiskaddr $fdtaddr"
977 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
979 #endif /* __CONFIG_H */