2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * QorIQ RDB boards configuration file
30 #define CONFIG_PHYS_64BIT
33 #if defined(CONFIG_P1020MBG)
34 #define CONFIG_BOARDNAME "P1020MBG-PC"
36 #define CONFIG_VSC7385_ENET
38 #define __SW_BOOT_MASK 0x03
39 #define __SW_BOOT_NOR 0xe4
40 #define __SW_BOOT_SD 0x54
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
44 #if defined(CONFIG_P1020UTM)
45 #define CONFIG_BOARDNAME "P1020UTM-PC"
47 #define __SW_BOOT_MASK 0x03
48 #define __SW_BOOT_NOR 0xe0
49 #define __SW_BOOT_SD 0x50
50 #define CONFIG_SYS_L2_SIZE (256 << 10)
53 #if defined(CONFIG_P1020RDB)
54 #define CONFIG_BOARDNAME "P1020RDB-PC"
55 #define CONFIG_NAND_FSL_ELBC
57 #define CONFIG_SPI_FLASH
58 #define CONFIG_VSC7385_ENET
60 #define __SW_BOOT_MASK 0x03
61 #define __SW_BOOT_NOR 0x5c
62 #define __SW_BOOT_SPI 0x1c
63 #define __SW_BOOT_SD 0x9c
64 #define __SW_BOOT_NAND 0xec
65 #define __SW_BOOT_PCIE 0x6c
66 #define CONFIG_SYS_L2_SIZE (256 << 10)
69 #if defined(CONFIG_P1021RDB)
70 #define CONFIG_BOARDNAME "P1021RDB-PC"
71 #define CONFIG_NAND_FSL_ELBC
74 #define CONFIG_SPI_FLASH
75 #define CONFIG_VSC7385_ENET
76 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
77 addresses in the LBC */
78 #define __SW_BOOT_MASK 0x03
79 #define __SW_BOOT_NOR 0x5c
80 #define __SW_BOOT_SPI 0x1c
81 #define __SW_BOOT_SD 0x9c
82 #define __SW_BOOT_NAND 0xec
83 #define __SW_BOOT_PCIE 0x6c
84 #define CONFIG_SYS_L2_SIZE (256 << 10)
87 #if defined(CONFIG_P1024RDB)
88 #define CONFIG_BOARDNAME "P1024RDB"
89 #define CONFIG_NAND_FSL_ELBC
92 #define CONFIG_SPI_FLASH
93 #define __SW_BOOT_MASK 0xf3
94 #define __SW_BOOT_NOR 0x00
95 #define __SW_BOOT_SPI 0x08
96 #define __SW_BOOT_SD 0x04
97 #define __SW_BOOT_NAND 0x0c
98 #define CONFIG_SYS_L2_SIZE (256 << 10)
101 #if defined(CONFIG_P1025RDB)
102 #define CONFIG_BOARDNAME "P1025RDB"
103 #define CONFIG_NAND_FSL_ELBC
107 #define CONFIG_SPI_FLASH
109 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
110 addresses in the LBC */
111 #define __SW_BOOT_MASK 0xf3
112 #define __SW_BOOT_NOR 0x00
113 #define __SW_BOOT_SPI 0x08
114 #define __SW_BOOT_SD 0x04
115 #define __SW_BOOT_NAND 0x0c
116 #define CONFIG_SYS_L2_SIZE (256 << 10)
119 #if defined(CONFIG_P2020RDB)
120 #define CONFIG_BOARDNAME "P2020RDB-PCA"
121 #define CONFIG_NAND_FSL_ELBC
123 #define CONFIG_SPI_FLASH
124 #define CONFIG_VSC7385_ENET
125 #define __SW_BOOT_MASK 0x03
126 #define __SW_BOOT_NOR 0xc8
127 #define __SW_BOOT_SPI 0x28
128 #define __SW_BOOT_SD 0x68 /* or 0x18 */
129 #define __SW_BOOT_NAND 0xe8
130 #define __SW_BOOT_PCIE 0xa8
131 #define CONFIG_SYS_L2_SIZE (512 << 10)
134 #if CONFIG_SYS_L2_SIZE >= (512 << 10)
136 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
137 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
138 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
142 #define CONFIG_RAMBOOT_SDCARD
143 #define CONFIG_SYS_RAMBOOT
144 #define CONFIG_SYS_EXTRA_ENV_RELOC
145 #define CONFIG_SYS_TEXT_BASE 0x11000000
146 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
149 #ifdef CONFIG_SPIFLASH
150 #define CONFIG_RAMBOOT_SPIFLASH
151 #define CONFIG_SYS_RAMBOOT
152 #define CONFIG_SYS_EXTRA_ENV_RELOC
153 #define CONFIG_SYS_TEXT_BASE 0x11000000
154 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
159 #define CONFIG_SPL_INIT_MINIMAL
160 #define CONFIG_SPL_SERIAL_SUPPORT
161 #define CONFIG_SPL_NAND_SUPPORT
162 #define CONFIG_SPL_NAND_MINIMAL
163 #define CONFIG_SPL_FLUSH_IMAGE
164 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
166 #define CONFIG_SPL_TEXT_BASE 0xfffff000
167 #define CONFIG_SPL_MAX_SIZE 4096
169 #ifdef CONFIG_SYS_INIT_L2_ADDR
170 /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
171 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
172 #define CONFIG_SPL_RELOC_TEXT_BASE \
173 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
174 #define CONFIG_SPL_RELOC_STACK \
175 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
176 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
177 #define CONFIG_SYS_NAND_U_BOOT_START \
178 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
180 #define CONFIG_SYS_TEXT_BASE 0x00201000
181 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
182 #define CONFIG_SPL_RELOC_STACK 0x00100000
183 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
184 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
187 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
188 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
189 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
192 #ifndef CONFIG_SYS_TEXT_BASE
193 #define CONFIG_SYS_TEXT_BASE 0xeff80000
196 #ifndef CONFIG_RESET_VECTOR_ADDRESS
197 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
200 #ifndef CONFIG_SYS_MONITOR_BASE
201 #ifdef CONFIG_SPL_BUILD
202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
208 /* High Level Configuration Options */
211 #define CONFIG_MPC85xx
215 #define CONFIG_FSL_ELBC
217 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
218 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
219 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
220 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
221 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
222 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
224 #define CONFIG_FSL_LAW
225 #define CONFIG_TSEC_ENET /* tsec ethernet support */
226 #define CONFIG_ENV_OVERWRITE
228 #define CONFIG_CMD_SATA
229 #define CONFIG_SATA_SIL
230 #define CONFIG_SYS_SATA_MAX_DEVICE 2
231 #define CONFIG_LIBATA
234 #if defined(CONFIG_P2020RDB)
235 #define CONFIG_SYS_CLK_FREQ 100000000
237 #define CONFIG_SYS_CLK_FREQ 66666666
239 #define CONFIG_DDR_CLK_FREQ 66666666
241 #define CONFIG_HWCONFIG
243 * These can be toggled for performance analysis, otherwise use default.
245 #define CONFIG_L2_CACHE
248 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
250 #define CONFIG_ENABLE_36BIT_PHYS
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_ADDR_MAP 1
254 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
257 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
258 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
259 #define CONFIG_PANIC_HANG /* do not reset board on panic */
261 #define CONFIG_SYS_CCSRBAR 0xffe00000
262 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
264 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
266 #ifdef CONFIG_SPL_BUILD
267 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
271 #define CONFIG_FSL_DDR3
272 #define CONFIG_SYS_DDR_RAW_TIMING
273 #define CONFIG_DDR_SPD
274 #define CONFIG_SYS_SPD_BUS_NUM 1
275 #define SPD_EEPROM_ADDRESS 0x52
276 #undef CONFIG_FSL_DDR_INTERACTIVE
278 #ifdef CONFIG_P1020MBG
279 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
280 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
282 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
283 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
285 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
286 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
287 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
289 #define CONFIG_NUM_DDR_CONTROLLERS 1
290 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
292 /* Default settings for DDR3 */
293 #ifndef CONFIG_P2020RDB
294 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
295 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
296 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
297 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
298 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
299 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
301 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
302 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
303 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
304 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
306 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
307 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
308 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
309 #define CONFIG_SYS_DDR_RCW_1 0x00000000
310 #define CONFIG_SYS_DDR_RCW_2 0x00000000
311 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
312 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
313 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
314 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
316 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
317 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
318 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
319 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
320 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
321 #define CONFIG_SYS_DDR_MODE_1 0x40461520
322 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
323 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
326 #undef CONFIG_CLOCKS_IN_MHZ
331 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
332 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
333 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
334 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
336 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
337 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
338 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
339 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
340 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
341 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
342 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
347 * Local Bus Definitions
349 #if defined(CONFIG_P1020MBG)
350 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
351 #define CONFIG_SYS_FLASH_BASE 0xec000000
352 #elif defined(CONFIG_P1020UTM)
353 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
354 #define CONFIG_SYS_FLASH_BASE 0xee000000
356 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
357 #define CONFIG_SYS_FLASH_BASE 0xef000000
361 #ifdef CONFIG_PHYS_64BIT
362 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
364 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
367 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
370 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
372 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
373 #define CONFIG_SYS_FLASH_QUIET_TEST
374 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
376 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
378 #undef CONFIG_SYS_FLASH_CHECKSUM
379 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
380 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
382 #define CONFIG_FLASH_CFI_DRIVER
383 #define CONFIG_SYS_FLASH_CFI
384 #define CONFIG_SYS_FLASH_EMPTY_INFO
385 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
388 #ifdef CONFIG_NAND_FSL_ELBC
389 #define CONFIG_SYS_NAND_BASE 0xff800000
390 #ifdef CONFIG_PHYS_64BIT
391 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
393 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
396 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
397 #define CONFIG_SYS_MAX_NAND_DEVICE 1
398 #define CONFIG_MTD_NAND_VERIFY_WRITE
399 #define CONFIG_CMD_NAND
400 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
402 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
403 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
404 | BR_PS_8 /* Port Size = 8 bit */ \
405 | BR_MS_FCM /* MSEL = FCM */ \
407 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
414 #endif /* CONFIG_NAND_FSL_ELBC */
416 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
418 #define CONFIG_SYS_INIT_RAM_LOCK
419 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
420 #ifdef CONFIG_PHYS_64BIT
421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
423 /* The assembler doesn't like typecast */
424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
425 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
426 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
428 /* Initial L1 address */
429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
433 /* Size of used area in RAM */
434 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
436 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
437 GENERATED_GBL_DATA_SIZE)
438 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
440 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
441 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
443 #define CONFIG_SYS_CPLD_BASE 0xffa00000
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
447 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
449 /* CPLD config size: 1Mb */
450 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
452 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
454 #define CONFIG_SYS_PMC_BASE 0xff980000
455 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
456 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
458 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
459 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
463 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
464 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
465 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
466 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
468 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
469 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
470 #ifdef CONFIG_NAND_FSL_ELBC
471 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
472 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
475 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
476 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
480 #ifdef CONFIG_VSC7385_ENET
481 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
483 #ifdef CONFIG_PHYS_64BIT
484 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
486 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
489 #define CONFIG_SYS_VSC7385_BR_PRELIM \
490 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
491 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
492 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
493 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
495 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
496 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
498 /* The size of the VSC7385 firmware image */
499 #define CONFIG_VSC7385_IMAGE_SIZE 8192
502 /* Serial Port - controlled on board with jumper J8
506 #define CONFIG_CONS_INDEX 1
507 #undef CONFIG_SERIAL_SOFTWARE_FIFO
508 #define CONFIG_SYS_NS16550
509 #define CONFIG_SYS_NS16550_SERIAL
510 #define CONFIG_SYS_NS16550_REG_SIZE 1
511 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
512 #ifdef CONFIG_SPL_BUILD
513 #define CONFIG_NS16550_MIN_FUNCTIONS
516 #define CONFIG_SYS_BAUDRATE_TABLE \
517 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
519 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
520 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
522 /* Use the HUSH parser */
523 #define CONFIG_SYS_HUSH_PARSER
526 * Pass open firmware flat tree
528 #define CONFIG_OF_LIBFDT
529 #define CONFIG_OF_BOARD_SETUP
530 #define CONFIG_OF_STDOUT_VIA_ALIAS
532 /* new uImage format support */
534 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
537 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
538 #define CONFIG_HARD_I2C /* I2C with hardware support */
539 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
540 #define CONFIG_I2C_MULTI_BUS
541 #define CONFIG_I2C_CMD_TREE
542 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */
543 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
544 #define CONFIG_SYS_I2C_SLAVE 0x7F
545 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */
546 #define CONFIG_SYS_I2C_OFFSET 0x3000
547 #define CONFIG_SYS_I2C2_OFFSET 0x3100
548 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
553 #undef CONFIG_ID_EEPROM
555 #define CONFIG_RTC_PT7C4338
556 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
557 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
559 /* enable read and write access to EEPROM */
560 #define CONFIG_CMD_EEPROM
561 #define CONFIG_SYS_I2C_MULTI_EEPROMS
562 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
563 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
564 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
567 * eSPI - Enhanced SPI
569 #define CONFIG_HARD_SPI
570 #define CONFIG_FSL_ESPI
572 #if defined(CONFIG_SPI_FLASH)
573 #define CONFIG_SPI_FLASH_SPANSION
574 #define CONFIG_CMD_SF
575 #define CONFIG_SF_DEFAULT_SPEED 10000000
576 #define CONFIG_SF_DEFAULT_MODE 0
579 #if defined(CONFIG_PCI)
582 * Memory space is mapped 1-1, but I/O space must start from 0.
585 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
586 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
587 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
588 #ifdef CONFIG_PHYS_64BIT
589 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
590 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
592 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
593 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
595 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
596 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
597 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
598 #ifdef CONFIG_PHYS_64BIT
599 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
601 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
603 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
605 /* controller 1, Slot 2, tgtid 1, Base address a000 */
606 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
607 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
608 #ifdef CONFIG_PHYS_64BIT
609 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
610 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
612 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
613 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
615 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
616 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
617 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
618 #ifdef CONFIG_PHYS_64BIT
619 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
621 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
623 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
625 #define CONFIG_PCI_PNP /* do pci plug-and-play */
626 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
627 #define CONFIG_CMD_PCI
628 #define CONFIG_CMD_NET
630 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
631 #define CONFIG_DOS_PARTITION
632 #endif /* CONFIG_PCI */
634 #if defined(CONFIG_TSEC_ENET)
635 #define CONFIG_MII /* MII PHY management */
637 #define CONFIG_TSEC1_NAME "eTSEC1"
639 #define CONFIG_TSEC2_NAME "eTSEC2"
641 #define CONFIG_TSEC3_NAME "eTSEC3"
643 #define TSEC1_PHY_ADDR 2
644 #define TSEC2_PHY_ADDR 0
645 #define TSEC3_PHY_ADDR 1
647 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
648 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
649 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
651 #define TSEC1_PHYIDX 0
652 #define TSEC2_PHYIDX 0
653 #define TSEC3_PHYIDX 0
655 #define CONFIG_ETHPRIME "eTSEC1"
657 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
659 #define CONFIG_HAS_ETH0
660 #define CONFIG_HAS_ETH1
661 #define CONFIG_HAS_ETH2
662 #endif /* CONFIG_TSEC_ENET */
665 /* QE microcode/firmware address */
666 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
667 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
668 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
669 #endif /* CONFIG_QE */
671 #ifdef CONFIG_P1025RDB
673 * QE UEC ethernet configuration
675 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
677 #undef CONFIG_UEC_ETH
678 #define CONFIG_PHY_MODE_NEED_CHANGE
680 #define CONFIG_UEC_ETH1 /* ETH1 */
681 #define CONFIG_HAS_ETH0
683 #ifdef CONFIG_UEC_ETH1
684 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
685 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
686 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
687 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
688 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
689 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
690 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
691 #endif /* CONFIG_UEC_ETH1 */
693 #define CONFIG_UEC_ETH5 /* ETH5 */
694 #define CONFIG_HAS_ETH1
696 #ifdef CONFIG_UEC_ETH5
697 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
698 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
699 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
700 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
701 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
702 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
703 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
704 #endif /* CONFIG_UEC_ETH5 */
705 #endif /* CONFIG_P1025RDB */
710 #ifdef CONFIG_RAMBOOT_SPIFLASH
711 #define CONFIG_ENV_IS_IN_SPI_FLASH
712 #define CONFIG_ENV_SPI_BUS 0
713 #define CONFIG_ENV_SPI_CS 0
714 #define CONFIG_ENV_SPI_MAX_HZ 10000000
715 #define CONFIG_ENV_SPI_MODE 0
716 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
717 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
718 #define CONFIG_ENV_SECT_SIZE 0x10000
719 #elif defined(CONFIG_RAMBOOT_SDCARD)
720 #define CONFIG_ENV_IS_IN_MMC
721 #define CONFIG_FSL_FIXED_MMC_LOCATION
722 #define CONFIG_ENV_SIZE 0x2000
723 #define CONFIG_SYS_MMC_ENV_DEV 0
724 #elif defined(CONFIG_NAND)
725 #define CONFIG_ENV_IS_IN_NAND
726 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
727 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
728 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
729 #elif defined(CONFIG_SYS_RAMBOOT)
730 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
731 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
732 #define CONFIG_ENV_SIZE 0x2000
734 #define CONFIG_ENV_IS_IN_FLASH
735 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
736 #define CONFIG_ENV_ADDR 0xfff80000
738 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
740 #define CONFIG_ENV_SIZE 0x2000
741 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
744 #define CONFIG_LOADS_ECHO /* echo on for serial download */
745 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
748 * Command line configuration.
750 #include <config_cmd_default.h>
752 #define CONFIG_CMD_IRQ
753 #define CONFIG_CMD_PING
754 #define CONFIG_CMD_I2C
755 #define CONFIG_CMD_MII
756 #define CONFIG_CMD_DATE
757 #define CONFIG_CMD_ELF
758 #define CONFIG_CMD_SETEXPR
759 #define CONFIG_CMD_REGINFO
764 #define CONFIG_HAS_FSL_DR_USB
766 #if defined(CONFIG_HAS_FSL_DR_USB)
767 #define CONFIG_USB_EHCI
769 #ifdef CONFIG_USB_EHCI
770 #define CONFIG_CMD_USB
771 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
772 #define CONFIG_USB_EHCI_FSL
773 #define CONFIG_USB_STORAGE
780 #define CONFIG_FSL_ESDHC
781 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
782 #define CONFIG_CMD_MMC
783 #define CONFIG_GENERIC_MMC
786 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
787 || defined(CONFIG_FSL_SATA)
788 #define CONFIG_CMD_EXT2
789 #define CONFIG_CMD_FAT
790 #define CONFIG_DOS_PARTITION
793 #undef CONFIG_WATCHDOG /* watchdog disabled */
796 * Miscellaneous configurable options
798 #define CONFIG_SYS_LONGHELP /* undef to save memory */
799 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
800 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
801 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
802 #if defined(CONFIG_CMD_KGDB)
803 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
805 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
807 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
808 /* Print Buffer Size */
809 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
810 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
811 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
814 * For booting Linux, the board info and command line data
815 * have to be in the first 64 MB of memory, since this is
816 * the maximum mapped by the Linux kernel during initialization.
818 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
819 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
821 #if defined(CONFIG_CMD_KGDB)
822 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
823 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
827 * Environment Configuration
829 #define CONFIG_HOSTNAME unknown
830 #define CONFIG_ROOTPATH "/opt/nfsroot"
831 #define CONFIG_BOOTFILE "uImage"
832 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
834 /* default location for tftp and bootm */
835 #define CONFIG_LOADADDR 1000000
837 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
838 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
840 #define CONFIG_BAUDRATE 115200
843 #define __NOR_RST_CMD \
844 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
845 i2c mw 18 3 __SW_BOOT_MASK 1; reset
848 #define __SPI_RST_CMD \
849 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
850 i2c mw 18 3 __SW_BOOT_MASK 1; reset
853 #define __SD_RST_CMD \
854 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
855 i2c mw 18 3 __SW_BOOT_MASK 1; reset
857 #ifdef __SW_BOOT_NAND
858 #define __NAND_RST_CMD \
859 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
860 i2c mw 18 3 __SW_BOOT_MASK 1; reset
862 #ifdef __SW_BOOT_PCIE
863 #define __PCIE_RST_CMD \
864 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
865 i2c mw 18 3 __SW_BOOT_MASK 1; reset
868 #define CONFIG_EXTRA_ENV_SETTINGS \
870 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
871 "loadaddr=1000000\0" \
872 "bootfile=uImage\0" \
873 "tftpflash=tftpboot $loadaddr $uboot; " \
874 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
875 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
876 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
877 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
878 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
879 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
880 "consoledev=ttyS0\0" \
881 "ramdiskaddr=2000000\0" \
882 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
885 "jffs2nor=mtdblock3\0" \
886 "norbootaddr=ef080000\0" \
887 "norfdtaddr=ef040000\0" \
888 "jffs2nand=mtdblock9\0" \
889 "nandbootaddr=100000\0" \
890 "nandfdtaddr=80000\0" \
891 "ramdisk_size=120000\0" \
892 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
893 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
894 __stringify(__NOR_RST_CMD)"\0" \
895 __stringify(__SPI_RST_CMD)"\0" \
896 __stringify(__SD_RST_CMD)"\0" \
897 __stringify(__NAND_RST_CMD)"\0" \
898 __stringify(__PCIE_RST_CMD)"\0"
900 #define CONFIG_NFSBOOTCOMMAND \
901 "setenv bootargs root=/dev/nfs rw " \
902 "nfsroot=$serverip:$rootpath " \
903 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
904 "console=$consoledev,$baudrate $othbootargs;" \
905 "tftp $loadaddr $bootfile;" \
906 "tftp $fdtaddr $fdtfile;" \
907 "bootm $loadaddr - $fdtaddr"
909 #define CONFIG_HDBOOT \
910 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
911 "console=$consoledev,$baudrate $othbootargs;" \
913 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
914 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
915 "bootm $loadaddr - $fdtaddr"
917 #define CONFIG_USB_FAT_BOOT \
918 "setenv bootargs root=/dev/ram rw " \
919 "console=$consoledev,$baudrate $othbootargs " \
920 "ramdisk_size=$ramdisk_size;" \
922 "fatload usb 0:2 $loadaddr $bootfile;" \
923 "fatload usb 0:2 $fdtaddr $fdtfile;" \
924 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
925 "bootm $loadaddr $ramdiskaddr $fdtaddr"
927 #define CONFIG_USB_EXT2_BOOT \
928 "setenv bootargs root=/dev/ram rw " \
929 "console=$consoledev,$baudrate $othbootargs " \
930 "ramdisk_size=$ramdisk_size;" \
932 "ext2load usb 0:4 $loadaddr $bootfile;" \
933 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
934 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
935 "bootm $loadaddr $ramdiskaddr $fdtaddr"
937 #define CONFIG_NORBOOT \
938 "setenv bootargs root=/dev/$jffs2nor rw " \
939 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
940 "bootm $norbootaddr - $norfdtaddr"
942 #define CONFIG_RAMBOOTCOMMAND \
943 "setenv bootargs root=/dev/ram rw " \
944 "console=$consoledev,$baudrate $othbootargs " \
945 "ramdisk_size=$ramdisk_size;" \
946 "tftp $ramdiskaddr $ramdiskfile;" \
947 "tftp $loadaddr $bootfile;" \
948 "tftp $fdtaddr $fdtfile;" \
949 "bootm $loadaddr $ramdiskaddr $fdtaddr"
951 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
953 #endif /* __CONFIG_H */