2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Eric Schumann, Phytec Messatechnik GmbH
9 * Jon Smirl <jonsmirl@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
17 #define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
19 /*-----------------------------------------------------------------------------
20 High Level Configuration Options
22 -----------------------------------------------------------------------------*/
23 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
24 #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25 #define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
32 * 0x00100000 boot from RAM (for testing only)
34 #ifndef CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
38 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
40 /*-----------------------------------------------------------------------------
41 Serial console configuration
42 -----------------------------------------------------------------------------*/
43 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
47 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
50 * Command line configuration.
52 #define CONFIG_CMD_PCI
54 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
56 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
57 #define CONFIG_SYS_LOWBOOT 1
59 /* RAMBOOT will be defined automatically in memory section */
61 #define CONFIG_JFFS2_CMDLINE
62 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
63 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
64 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
66 #undef CONFIG_BOOTARGS
68 #define CONFIG_PREBOOT "echo;" \
69 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
70 "mount root filesystem over NFS;" \
73 #define CONFIG_EXTRA_ENV_SETTINGS \
75 "uimage=uImage-pcm030\0" \
76 "oftree=oftree-pcm030.dtb\0" \
77 "jffs2=root-pcm030.jffs2\0" \
78 "uboot=u-boot-pcm030.bin\0" \
79 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
81 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
82 " rootfstype=jffs2\0" \
83 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
84 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
85 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
86 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
87 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
88 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
90 " cp.b 0x400000 0xff040000 $(filesize)\0" \
91 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
92 "cp.b 0x400000 0xff200000 $(filesize)\0" \
93 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
94 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
95 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
96 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
100 #define CONFIG_BOOTCOMMAND "run bcmd_flash"
102 /*--------------------------------------------------------------------------
103 IPB Bus clocking configuration.
104 ---------------------------------------------------------------------------*/
105 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
107 /*-------------------------------------------------------------------------
109 * 0x40000000 - 0x4fffffff - PCI Memory
110 * 0x50000000 - 0x50ffffff - PCI IO Space
111 * -----------------------------------------------------------------------*/
112 #define CONFIG_PCI_SCAN_SHOW 1
113 #define CONFIG_PCI_MEM_BUS 0x40000000
114 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
115 #define CONFIG_PCI_MEM_SIZE 0x10000000
116 #define CONFIG_PCI_IO_BUS 0x50000000
117 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
118 #define CONFIG_PCI_IO_SIZE 0x01000000
119 #define CONFIG_SYS_XLB_PIPELINING 1
121 /*---------------------------------------------------------------------------
123 ---------------------------------------------------------------------------*/
125 #define CONFIG_SYS_FLASH_BASE 0xff000000
126 #define CONFIG_SYS_FLASH_SIZE 0x01000000
127 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
129 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
130 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
131 #define CONFIG_SYS_FLASH_EMPTY_INFO
132 #define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
134 /* (= chip selects) */
135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
138 * Use also hardware protection. This seems required, as the BDI uses
139 * hardware protection. Without this, U-Boot can't work with this sectors,
140 * as its protection is software only by default
142 #define CONFIG_SYS_FLASH_PROTECTION 1
144 /*---------------------------------------------------------------------------
146 ---------------------------------------------------------------------------*/
148 #define CONFIG_ENV_IS_NOWHERE
149 #define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
150 /*beginning of the EEPROM */
151 #define CONFIG_ENV_SIZE 2048
153 #define CONFIG_ENV_OVERWRITE 1
155 /*-----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------*/
158 #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
159 /* bootloader or debugger config */
160 #define CONFIG_SYS_SDRAM_BASE 0x00000000
161 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
162 /* Use SRAM until RAM will be available */
163 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
164 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
166 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
167 GENERATED_GBL_DATA_SIZE)
168 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
171 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
172 # define CONFIG_SYS_RAMBOOT 1
175 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
176 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
177 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
179 /*-----------------------------------------------------------------------------
180 Ethernet configuration
181 -----------------------------------------------------------------------------*/
182 #define CONFIG_MPC5xxx_FEC 1
183 #define CONFIG_MPC5xxx_FEC_MII100
184 #define CONFIG_PHY_ADDR 0x01
186 /*---------------------------------------------------------------------------
188 ---------------------------------------------------------------------------*/
190 /* GPIO port configuration
195 * PSC1_0 -> AC97 SDATA out
196 * PSC1_1 -> AC97 SDTA in
197 * PSC1_2 -> AC97 SYNC out
198 * PSC1_3 -> AC97 bitclock out
199 * PSC1_4 -> AC97 reset out
202 * PSC2_0 -> CAN 1 Tx out
203 * PSC2_1 -> CAN 1 Rx in
204 * PSC2_2 -> CAN 2 Tx out
205 * PSC2_3 -> CAN 2 Rx in
206 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
210 * PSC3_0 -> UART Tx out
211 * PSC3_1 -> UART Rx in
212 * PSC3_2 -> UART RTS (in/out FIXME)
213 * PSC3_3 -> UART CTS (in/out FIXME)
214 * PSC3_4 -> LocalPlus Bus CS6 \
215 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
216 * PSC3_6 -> dedicated SPI MOSI out (master case)
217 * PSC3_7 -> dedicated SPI MISO in (master case)
218 * PSC3_8 -> dedicated SPI SS out (master case)
219 * PSC3_9 -> dedicated SPI CLK out (master case)
222 * USB_0 -> USB OE out
223 * USB_1 -> USB Tx- out
224 * USB_2 -> USB Tx+ out
225 * USB_3 -> USB RxD (in/out FIXME)
226 * USB_4 -> USB Rx+ in
227 * USB_5 -> USB Rx- in
228 * USB_6 -> USB PortPower out
229 * USB_7 -> USB speed out
230 * USB_8 -> USB suspend (in/out FIXME)
231 * USB_9 -> USB overcurrent in
234 * USB differential mode
250 * ETH_10 -> ETH Collision
256 * ETH_16 -> ETH Rxerr
260 * PSC6_0 -> UART RxD in
261 * PSC6_1 -> UART CTS (in/out FIXME)
262 * PSC6_2 -> UART TxD out
263 * PSC6_3 -> UART RTS (in/out FIXME)
266 * TMR_0 -> ATA_CS0 out
267 * TMR_1 -> ATA_CS1 out
274 * I2C_0 -> I2C 1 Clock out
275 * I2C_1 -> I2C 1 IO in/out
276 * I2C_2 -> I2C 2 Clock out
277 * I2C_3 -> I2C 2 IO in/out
280 * PSC3_5 is used as CS7
283 * PSC3_4 is used as CS6
286 * gpio_wkup_7 is GPIO
289 * gpio_wkup_6 is GPIO
292 #define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
294 /*-----------------------------------------------------------------------------
295 Miscellaneous configurable options
296 -------------------------------------------------------------------------------*/
297 #define CONFIG_SYS_LONGHELP /* undef to save memory */
299 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
301 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
302 #if defined(CONFIG_CMD_KGDB)
303 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
306 #if defined(CONFIG_CMD_KGDB)
307 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
309 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
311 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
312 /* Print Buffer Size */
313 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
314 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
316 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
317 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
319 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
321 /*-----------------------------------------------------------------------------
322 Various low-level settings
323 -----------------------------------------------------------------------------*/
324 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
325 #define CONFIG_SYS_HID0_FINAL HID0_ICE
327 /* no burst access on the LPB */
328 #define CONFIG_SYS_CS_BURST 0x00000000
329 /* one deadcycle for the 33MHz statemachine */
330 #define CONFIG_SYS_CS_DEADCYCLE 0x33333331
331 /* one additional waitstate for the 33MHz statemachine */
332 #define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
333 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
334 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
336 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
338 /*-----------------------------------------------------------------------
340 *-----------------------------------------------------------------------
342 #define CONFIG_USB_CLOCK 0x0001BBBB
343 #define CONFIG_USB_CONFIG 0x00001000
345 /*---------------------------------------------------------------------------
346 IDE/ATA stuff Supports IDE harddisk
347 ----------------------------------------------------------------------------*/
349 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
350 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
351 #undef CONFIG_IDE_LED /* LED for ide not supported */
352 #define CONFIG_SYS_ATA_CS_ON_TIMER01
353 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
354 #define CONFIG_IDE_PREINIT
355 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
356 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
357 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
358 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
359 /* Offset for data I/O */
360 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
361 /* Offset for normal register accesses */
362 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
363 /* Offset for alternate registers */
364 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
365 /* Interval between registers */
366 #define CONFIG_SYS_ATA_STRIDE 4
367 #define CONFIG_ATAPI 1
370 #define CONFIG_USB_OHCI
372 /* pass open firmware flat tree */
373 #define OF_CPU "PowerPC,5200@0"
374 #define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
375 #define OF_SOC "soc5200@f0000000"
376 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
378 #endif /* __CONFIG_H */