2 * (C) Copyright 2009-2010
3 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * pdm360ng board configuration file
15 #define CONFIG_PDM360NG 1
16 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_SYS_GENERIC_BOARD
20 * Memory map for the PDM360NG board:
22 * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
23 * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB)
24 * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB)
25 * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB)
26 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
27 * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB)
28 * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional
32 * High Level Configuration Options
34 #define CONFIG_E300 1 /* E300 Family */
35 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
37 #define CONFIG_SYS_TEXT_BASE 0xF0000000
39 /* Used for silent command in environment */
40 #define CONFIG_SYS_DEVICE_NULLDEV
41 #define CONFIG_SILENT_CONSOLE
46 #if defined(CONFIG_VIDEO)
47 #define CONFIG_CFB_CONSOLE
48 #define CONFIG_VGA_AS_SINGLE_DEVICE
49 #define CONFIG_SPLASH_SCREEN
50 #define CONFIG_VIDEO_LOGO
51 #define CONFIG_VIDEO_BMP_RLE8
54 #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
56 #define CONFIG_MISC_INIT_R
58 #define CONFIG_SYS_IMMR 0x80000000
59 #define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
65 /* DDR is system memory */
66 #define CONFIG_SYS_DDR_BASE 0x00000000
67 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
68 #define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
70 /* DDR pin mux and slew rate */
71 #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012
73 /* Manually set all parameters as there's no SPD etc. */
75 * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
78 * [31:31] MDDRC Soft Reset: Diabled
79 * [30:30] DRAM CKE pin: Enabled
80 * [29:29] DRAM CLK: Enabled
81 * [28:28] Command Mode: Enabled (For initialization only)
82 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
83 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
84 * [20:19] Read Test: DON'T USE
85 * [18:18] Self Refresh: Enabled
86 * [17:17] 16bit Mode: Disabled
87 * [16:13] Read Delay: 3
88 * [12:12] Half DQS Delay: Disabled
89 * [11:11] Quarter DQS Delay: Disabled
90 * [10:08] Write Delay: 2
91 * [07:07] Early ODT: Disabled
92 * [06:06] On DIE Termination: Enabled
93 * [05:05] FIFO Overflow Clear: DON'T USE here
94 * [04:04] FIFO Underflow Clear: DON'T USE here
95 * [03:03] FIFO Overflow Pending: DON'T USE here
96 * [02:02] FIFO Underlfow Pending: DON'T USE here
97 * [01:01] FIFO Overlfow Enabled: Enabled
98 * [00:00] FIFO Underflow Enabled: Enabled
100 * [31:16] DRAM Refresh Time: 0 CSB clocks
101 * [15:8] DRAM Command Time: 0 CSB clocks
102 * [07:00] DRAM Precharge Time: 0 CSB clocks
106 * [20:17] DRAM tWRT1:
113 * [22:19] DRAM tRTW1:
119 #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
120 #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
121 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
122 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
125 * Alternative 1: small RAM (128 MB) configuration
127 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40
128 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
129 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
130 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
132 #define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
134 #define CONFIG_SYS_DDRCMD_NOP 0x01380000
135 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
136 #define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */
137 #define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */
138 /* EMR with 150 ohm ODT todo: verify */
139 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040
140 #define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
141 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
142 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
143 /* EMR with 150 ohm ODT todo: verify */
144 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0
145 /* EMR new command with 150 ohm ODT todo: verify */
146 #define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440
148 /* DDR Priority Manager Configuration */
149 #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
150 #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
151 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
152 #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
153 #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
154 #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
155 #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
156 #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
157 #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
158 #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
159 #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
160 #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
161 #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
162 #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
163 #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
164 #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
165 #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
166 #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
167 #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
168 #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
169 #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
170 #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
171 #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
174 * NOR FLASH on the Local Bus
176 #define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */
177 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
180 #define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
181 #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */
182 /* start of FLASH-Bank1 */
183 #define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \
184 CONFIG_SYS_FLASH_SIZE)
185 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
187 #define CONFIG_SYS_FLASH_BANKS_LIST \
188 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
190 #define CONFIG_SYS_SRAM_BASE 0x50000000
191 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
193 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE
194 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
196 /* ALE active low, data size 4 bytes */
197 #define CONFIG_SYS_CS0_CFG 0x05059350
198 /* ALE active low, data size 4 bytes */
199 #define CONFIG_SYS_CS1_CFG 0x05059350
201 #define CONFIG_SYS_MRAM_BASE 0x50040000
202 #define CONFIG_SYS_MRAM_SIZE 0x00020000
203 #define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE
204 #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE
206 /* ALE active low, data size 4 bytes */
207 #define CONFIG_SYS_CS2_CFG 0x05059110
209 /* alt. CS timing for CS0, CS1, CS2 */
210 #define CONFIG_SYS_CS_ALETIMING 0x00000007
215 #define CONFIG_CMD_NAND /* enable NAND support */
216 #define CONFIG_NAND_MPC5121_NFC
217 #define CONFIG_SYS_NAND_BASE 0x40000000
218 #define CONFIG_SYS_MAX_NAND_DEVICE 1
219 #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
222 * Configuration parameters for MPC5121 NAND driver
224 #define CONFIG_FSL_NFC_WIDTH 1
225 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
226 #define CONFIG_FSL_NFC_SPARE_SIZE 64
227 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
230 * Dynamic MTD partition support
232 #define CONFIG_CMD_MTDPARTS
233 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
234 #define CONFIG_FLASH_CFI_MTD
235 #define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
241 #define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
242 "256k(environment1)," \
243 "256k(environment2)," \
244 "256k(splash-factory)," \
245 "2m(FIT: recovery)," \
246 "4608k(fs-recovery)," \
247 "256k(splash-customer),"\
248 "5m(FIT: kernel+dtb)," \
249 "64m(rootfs squash)ro," \
251 "f8000000.flash:-(unused);" \
252 "MPC5121 NAND:1024m(extended-userfs)"
255 * Override partitions in device tree using info
256 * in "mtdparts" environment variable
258 #ifdef CONFIG_CMD_MTDPARTS
259 #define CONFIG_FDT_FIXUP_PARTITIONS
262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
263 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
264 #ifdef CONFIG_FSL_DIU_FB
265 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */
267 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
273 #define CONFIG_CONS_INDEX 1
276 * Serial console configuration
278 #define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
279 #if CONFIG_PSC_CONSOLE != 6
280 #error CONFIG_PSC_CONSOLE must be 6
283 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
284 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
285 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
286 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
291 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
292 CLOCK_SCCR1_LPC_EN | \
293 CLOCK_SCCR1_NFC_EN | \
294 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
295 CLOCK_SCCR1_PSCFIFO_EN | \
296 CLOCK_SCCR1_DDR_EN | \
297 CLOCK_SCCR1_FEC_EN | \
300 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
301 CLOCK_SCCR2_SPDIF_EN | \
302 CLOCK_SCCR2_DIU_EN | \
306 * Used PSC UART devices
308 #define CONFIG_SYS_PSC1
309 #define CONFIG_SYS_PSC4
310 #define CONFIG_SYS_PSC6
313 * Co-processor communication parameters
315 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
316 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
321 #define CONFIG_HARD_I2C /* I2C with hardware support */
322 #define CONFIG_I2C_MULTI_BUS
323 #define CONFIG_I2C_CMD_TREE
324 /* I2C speed and slave address */
325 #define CONFIG_SYS_I2C_SPEED 100000
326 #define CONFIG_SYS_I2C_SLAVE 0x7F
329 * IIM - IC Identification Module
331 #undef CONFIG_FSL_IIM
334 * EEPROM configuration
336 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */
337 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */
338 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */
344 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
345 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
347 * Enabled only to delete "ethaddr" before testing
348 * "ethaddr" setting from EEPROM
350 #define CONFIG_ENV_OVERWRITE
353 * Ethernet configuration
355 #define CONFIG_MPC512x_FEC 1
356 #define CONFIG_PHY_ADDR 0x1F
357 #define CONFIG_MII 1 /* MII PHY management */
358 #define CONFIG_FEC_AN_TIMEOUT 1
359 #define CONFIG_HAS_ETH0
362 * Configure on-board RTC
364 #define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */
365 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
370 #define CONFIG_ENV_IS_IN_FLASH 1
371 /* This has to be a multiple of the Flash sector size */
372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
373 CONFIG_SYS_MONITOR_LEN)
374 #define CONFIG_ENV_SIZE 0x2000
375 #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
377 /* Address and size of Redundant Environment Sector */
378 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
379 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
381 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
382 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
384 #include <config_cmd_default.h>
386 #define CONFIG_CMD_ASKENV
387 #define CONFIG_CMD_DATE
388 #define CONFIG_CMD_DHCP
389 #define CONFIG_CMD_EEPROM
390 #define CONFIG_CMD_I2C
391 #define CONFIG_CMD_MII
392 #define CONFIG_CMD_PING
393 #define CONFIG_CMD_REGINFO
395 #undef CONFIG_CMD_FUSE
398 #define CONFIG_CMD_BMP
402 * Miscellaneous configurable options
404 #define CONFIG_SYS_LONGHELP /* undef to save memory */
405 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
407 #ifdef CONFIG_CMD_KGDB
408 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
410 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
413 /* Print Buffer Size */
414 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
415 /* Max number of command args */
416 #define CONFIG_SYS_MAXARGS 16
417 /* Boot Argument Buffer Size */
418 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
419 /* Decrementer freq: 1ms ticks */
422 * For booting Linux, the board info and command line data
423 * have to be in the first 256 MB of memory, since this is
424 * the maximum mapped by the Linux kernel during initialization.
426 /* Initial Memory map for Linux */
427 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
429 /* Cache Configuration */
430 #define CONFIG_SYS_DCACHE_SIZE 32768
431 #define CONFIG_SYS_CACHELINE_SIZE 32
432 #ifdef CONFIG_CMD_KGDB
433 /* log base 2 of the above value */
434 #define CONFIG_SYS_CACHELINE_SHIFT 5
437 #define CONFIG_SYS_HID0_INIT 0x000000000
438 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
439 #define CONFIG_SYS_HID2 HID2_HBE
441 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
443 #ifdef CONFIG_CMD_KGDB
444 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
448 #define CONFIG_POST (CONFIG_SYS_POST_COPROC)
451 * Environment Configuration
453 #define CONFIG_TIMESTAMP
455 #define CONFIG_HOSTNAME pdm360ng
456 /* default location for tftp and bootm */
457 #define CONFIG_LOADADDR 400000
459 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
461 #define CONFIG_PREBOOT "echo;" \
462 "echo PDM360NG SAMPLE;" \
465 #define CONFIG_BOOTCOMMAND "run env_cont"
467 #define CONFIG_OF_LIBFDT 1
468 #define CONFIG_OF_BOARD_SETUP 1
469 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
471 #define CONFIG_FIT_VERBOSE
473 #define OF_CPU "PowerPC,5121@0"
474 #define OF_SOC_COMPAT "fsl,mpc5121-immr"
475 #define OF_TBCLK (bd->bi_busfreq / 4)
476 #define OF_STDOUT_PATH "/soc@80000000/serial@11600"
479 * Include common options for all mpc5121 boards
481 #include "mpc5121-common.h"
483 #endif /* __CONFIG_H */