2 * (C) Copyright 2009-2010
3 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * pdm360ng board configuration file
15 #define CONFIG_PDM360NG 1
18 * Memory map for the PDM360NG board:
20 * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
21 * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB)
22 * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB)
23 * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB)
24 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
25 * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB)
26 * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional
30 * High Level Configuration Options
32 #define CONFIG_E300 1 /* E300 Family */
33 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
35 #define CONFIG_SYS_TEXT_BASE 0xF0000000
37 /* Used for silent command in environment */
38 #define CONFIG_SYS_DEVICE_NULLDEV
39 #define CONFIG_SILENT_CONSOLE
44 #if defined(CONFIG_VIDEO)
45 #define CONFIG_CFB_CONSOLE
46 #define CONFIG_VGA_AS_SINGLE_DEVICE
47 #define CONFIG_SPLASH_SCREEN
48 #define CONFIG_VIDEO_LOGO
49 #define CONFIG_VIDEO_BMP_RLE8
52 #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
54 #define CONFIG_MISC_INIT_R
56 #define CONFIG_SYS_IMMR 0x80000000
57 #define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
63 /* DDR is system memory */
64 #define CONFIG_SYS_DDR_BASE 0x00000000
65 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
66 #define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
68 /* DDR pin mux and slew rate */
69 #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012
71 /* Manually set all parameters as there's no SPD etc. */
73 * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
76 * [31:31] MDDRC Soft Reset: Diabled
77 * [30:30] DRAM CKE pin: Enabled
78 * [29:29] DRAM CLK: Enabled
79 * [28:28] Command Mode: Enabled (For initialization only)
80 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
81 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
82 * [20:19] Read Test: DON'T USE
83 * [18:18] Self Refresh: Enabled
84 * [17:17] 16bit Mode: Disabled
85 * [16:13] Read Delay: 3
86 * [12:12] Half DQS Delay: Disabled
87 * [11:11] Quarter DQS Delay: Disabled
88 * [10:08] Write Delay: 2
89 * [07:07] Early ODT: Disabled
90 * [06:06] On DIE Termination: Enabled
91 * [05:05] FIFO Overflow Clear: DON'T USE here
92 * [04:04] FIFO Underflow Clear: DON'T USE here
93 * [03:03] FIFO Overflow Pending: DON'T USE here
94 * [02:02] FIFO Underlfow Pending: DON'T USE here
95 * [01:01] FIFO Overlfow Enabled: Enabled
96 * [00:00] FIFO Underflow Enabled: Enabled
98 * [31:16] DRAM Refresh Time: 0 CSB clocks
99 * [15:8] DRAM Command Time: 0 CSB clocks
100 * [07:00] DRAM Precharge Time: 0 CSB clocks
104 * [20:17] DRAM tWRT1:
111 * [22:19] DRAM tRTW1:
117 #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
118 #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
119 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
120 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
123 * Alternative 1: small RAM (128 MB) configuration
125 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40
126 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
127 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
128 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
130 #define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
132 #define CONFIG_SYS_DDRCMD_NOP 0x01380000
133 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
134 #define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */
135 #define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */
136 /* EMR with 150 ohm ODT todo: verify */
137 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040
138 #define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
139 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
140 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
141 /* EMR with 150 ohm ODT todo: verify */
142 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0
143 /* EMR new command with 150 ohm ODT todo: verify */
144 #define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440
146 /* DDR Priority Manager Configuration */
147 #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
148 #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
149 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
150 #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
151 #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
152 #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
153 #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
154 #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
155 #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
156 #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
157 #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
158 #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
159 #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
160 #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
161 #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
162 #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
163 #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
164 #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
165 #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
166 #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
167 #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
168 #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
169 #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
172 * NOR FLASH on the Local Bus
174 #define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */
175 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
178 #define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
179 #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */
180 /* start of FLASH-Bank1 */
181 #define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \
182 CONFIG_SYS_FLASH_SIZE)
183 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
185 #define CONFIG_SYS_FLASH_BANKS_LIST \
186 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
188 #define CONFIG_SYS_SRAM_BASE 0x50000000
189 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
191 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE
192 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
194 /* ALE active low, data size 4 bytes */
195 #define CONFIG_SYS_CS0_CFG 0x05059350
196 /* ALE active low, data size 4 bytes */
197 #define CONFIG_SYS_CS1_CFG 0x05059350
199 #define CONFIG_SYS_MRAM_BASE 0x50040000
200 #define CONFIG_SYS_MRAM_SIZE 0x00020000
201 #define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE
202 #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE
204 /* ALE active low, data size 4 bytes */
205 #define CONFIG_SYS_CS2_CFG 0x05059110
207 /* alt. CS timing for CS0, CS1, CS2 */
208 #define CONFIG_SYS_CS_ALETIMING 0x00000007
213 #define CONFIG_CMD_NAND /* enable NAND support */
214 #define CONFIG_NAND_MPC5121_NFC
215 #define CONFIG_SYS_NAND_BASE 0x40000000
216 #define CONFIG_SYS_MAX_NAND_DEVICE 1
217 #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
220 * Configuration parameters for MPC5121 NAND driver
222 #define CONFIG_FSL_NFC_WIDTH 1
223 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
224 #define CONFIG_FSL_NFC_SPARE_SIZE 64
225 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
228 * Dynamic MTD partition support
230 #define CONFIG_CMD_MTDPARTS
231 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
232 #define CONFIG_FLASH_CFI_MTD
233 #define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
239 #define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
240 "256k(environment1)," \
241 "256k(environment2)," \
242 "256k(splash-factory)," \
243 "2m(FIT: recovery)," \
244 "4608k(fs-recovery)," \
245 "256k(splash-customer),"\
246 "5m(FIT: kernel+dtb)," \
247 "64m(rootfs squash)ro," \
249 "f8000000.flash:-(unused);" \
250 "MPC5121 NAND:1024m(extended-userfs)"
252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
253 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
254 #ifdef CONFIG_FSL_DIU_FB
255 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */
257 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
263 #define CONFIG_CONS_INDEX 1
266 * Serial console configuration
268 #define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
269 #if CONFIG_PSC_CONSOLE != 6
270 #error CONFIG_PSC_CONSOLE must be 6
273 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
274 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
275 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
276 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
281 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
282 CLOCK_SCCR1_LPC_EN | \
283 CLOCK_SCCR1_NFC_EN | \
284 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
285 CLOCK_SCCR1_PSCFIFO_EN | \
286 CLOCK_SCCR1_DDR_EN | \
287 CLOCK_SCCR1_FEC_EN | \
290 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
291 CLOCK_SCCR2_SPDIF_EN | \
292 CLOCK_SCCR2_DIU_EN | \
296 * Used PSC UART devices
298 #define CONFIG_SYS_PSC1
299 #define CONFIG_SYS_PSC4
300 #define CONFIG_SYS_PSC6
303 * Co-processor communication parameters
305 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
306 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
311 #define CONFIG_HARD_I2C /* I2C with hardware support */
312 #define CONFIG_I2C_MULTI_BUS
313 #define CONFIG_I2C_CMD_TREE
314 /* I2C speed and slave address */
315 #define CONFIG_SYS_I2C_SPEED 100000
316 #define CONFIG_SYS_I2C_SLAVE 0x7F
319 * IIM - IC Identification Module
321 #undef CONFIG_FSL_IIM
324 * EEPROM configuration
326 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */
327 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */
328 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */
334 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
335 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
337 * Enabled only to delete "ethaddr" before testing
338 * "ethaddr" setting from EEPROM
340 #define CONFIG_ENV_OVERWRITE
343 * Ethernet configuration
345 #define CONFIG_MPC512x_FEC 1
346 #define CONFIG_PHY_ADDR 0x1F
347 #define CONFIG_MII 1 /* MII PHY management */
348 #define CONFIG_FEC_AN_TIMEOUT 1
349 #define CONFIG_HAS_ETH0
352 * Configure on-board RTC
354 #define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */
355 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
360 #define CONFIG_ENV_IS_IN_FLASH 1
361 /* This has to be a multiple of the Flash sector size */
362 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
363 CONFIG_SYS_MONITOR_LEN)
364 #define CONFIG_ENV_SIZE 0x2000
365 #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
367 /* Address and size of Redundant Environment Sector */
368 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
369 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
371 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
372 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
374 #define CONFIG_CMD_DATE
375 #define CONFIG_CMD_EEPROM
376 #define CONFIG_CMD_REGINFO
378 #undef CONFIG_CMD_FUSE
381 #define CONFIG_CMD_BMP
385 * Miscellaneous configurable options
387 #define CONFIG_SYS_LONGHELP /* undef to save memory */
388 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
390 #ifdef CONFIG_CMD_KGDB
391 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
393 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
396 /* Print Buffer Size */
397 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
398 /* Max number of command args */
399 #define CONFIG_SYS_MAXARGS 16
400 /* Boot Argument Buffer Size */
401 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
402 /* Decrementer freq: 1ms ticks */
405 * For booting Linux, the board info and command line data
406 * have to be in the first 256 MB of memory, since this is
407 * the maximum mapped by the Linux kernel during initialization.
409 /* Initial Memory map for Linux */
410 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
412 /* Cache Configuration */
413 #define CONFIG_SYS_DCACHE_SIZE 32768
414 #define CONFIG_SYS_CACHELINE_SIZE 32
415 #ifdef CONFIG_CMD_KGDB
416 /* log base 2 of the above value */
417 #define CONFIG_SYS_CACHELINE_SHIFT 5
420 #define CONFIG_SYS_HID0_INIT 0x000000000
421 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
422 #define CONFIG_SYS_HID2 HID2_HBE
424 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
426 #ifdef CONFIG_CMD_KGDB
427 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
431 #define CONFIG_POST (CONFIG_SYS_POST_COPROC)
434 * Environment Configuration
436 #define CONFIG_TIMESTAMP
438 #define CONFIG_HOSTNAME pdm360ng
439 /* default location for tftp and bootm */
440 #define CONFIG_LOADADDR 400000
443 #define CONFIG_PREBOOT "echo;" \
444 "echo PDM360NG SAMPLE;" \
447 #define CONFIG_BOOTCOMMAND "run env_cont"
449 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
451 #define OF_CPU "PowerPC,5121@0"
452 #define OF_SOC_COMPAT "fsl,mpc5121-immr"
453 #define OF_TBCLK (bd->bi_busfreq / 4)
454 #define OF_STDOUT_PATH "/soc@80000000/serial@11600"
457 * Include common options for all mpc5121 boards
459 #include "mpc5121-common.h"
461 #endif /* __CONFIG_H */