1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 NXP Semiconductors
5 * Configuration settings for the i.MX7D Pico board.
8 #ifndef __PICO_IMX7D_CONFIG_H
9 #define __PICO_IMX7D_CONFIG_H
11 #include "mx7_common.h"
13 #define PHYS_SDRAM_SIZE SZ_1G
15 /* Size of malloc() pool */
16 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
18 #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
21 #define CONFIG_FEC_MXC
23 #define CONFIG_FEC_XCV_TYPE RGMII
24 #define CONFIG_ETHPRIME "FEC"
25 #define CONFIG_FEC_MXC_PHYADDR 1
27 #define CONFIG_PHY_ATHEROS
30 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
35 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
36 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
38 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "fdt_high=0xffffffff\0" \
43 "initrd_high=0xffffffff\0" \
44 "fdt_file=imx7d-pico-pi.dtb\0" \
45 "fdt_addr=0x83000000\0" \
47 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
48 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
49 "finduuid=part uuid mmc 0:2 uuid\0" \
50 "mmcargs=setenv bootargs console=${console},${baudrate} " \
51 "root=PARTUUID=${uuid} rootwait rw\0" \
52 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
53 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
54 "mmcboot=echo Booting from mmc ...; " \
57 "if run loadfdt; then " \
58 "bootz ${loadaddr} - ${fdt_addr}; " \
60 "echo WARN: Cannot load the DT; " \
62 "netargs=setenv bootargs console=${console},${baudrate} " \
64 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
65 "netboot=echo Booting from net ...; " \
67 "if test ${ip_dyn} = yes; then " \
68 "setenv get_cmd dhcp; " \
70 "setenv get_cmd tftp; " \
72 "${get_cmd} ${image}; " \
73 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
74 "bootz ${loadaddr} - ${fdt_addr}; " \
76 "echo WARN: Cannot load the DT; " \
79 #define CONFIG_BOOTCOMMAND \
80 "if mmc rescan; then " \
81 "if run loadimage; then " \
83 "else run netboot; " \
85 "else run netboot; fi"
87 #define CONFIG_SYS_MEMTEST_START 0x80000000
88 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
90 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
91 #define CONFIG_SYS_HZ 1000
93 /* Physical Memory Map */
94 #define CONFIG_NR_DRAM_BANKS 1
95 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
97 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
98 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
99 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
101 #define CONFIG_SYS_INIT_SP_OFFSET \
102 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_ADDR \
104 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
107 #define CONFIG_SYS_I2C
108 #define CONFIG_SYS_I2C_MXC
109 #define CONFIG_SYS_I2C_MXC_I2C1
110 #define CONFIG_SYS_I2C_MXC_I2C2
111 #define CONFIG_SYS_I2C_MXC_I2C3
112 #define CONFIG_SYS_I2C_MXC_I2C4
113 #define CONFIG_SYS_I2C_SPEED 100000
117 #define CONFIG_POWER_I2C
118 #define CONFIG_POWER_PFUZE3000
119 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
121 /* FLASH and environment organization */
122 #define CONFIG_ENV_SIZE SZ_8K
124 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
125 #define CONFIG_SYS_FSL_USDHC_NUM 2
127 #define CONFIG_SYS_MMC_ENV_DEV 0
128 #define CONFIG_SYS_MMC_ENV_PART 0
131 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
132 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
133 #define CONFIG_MXC_USB_FLAGS 0
134 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
136 #define CONFIG_IMX_THERMAL