2 * Copyright (C) 2017 NXP Semiconductors
4 * Configuration settings for the i.MX7D Pico board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __PICO_IMX7D_CONFIG_H
10 #define __PICO_IMX7D_CONFIG_H
12 #include "mx7_common.h"
14 #define PHYS_SDRAM_SIZE SZ_1G
16 /* Size of malloc() pool */
17 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
19 #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
22 #define CONFIG_FEC_MXC
24 #define CONFIG_FEC_XCV_TYPE RGMII
25 #define CONFIG_ETHPRIME "FEC"
26 #define CONFIG_FEC_MXC_PHYADDR 1
29 #define CONFIG_PHY_ATHEROS
32 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
37 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
38 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
40 #define CONFIG_EXTRA_ENV_SETTINGS \
44 "fdt_high=0xffffffff\0" \
45 "initrd_high=0xffffffff\0" \
46 "fdt_file=imx7d-pico.dtb\0" \
47 "fdt_addr=0x83000000\0" \
49 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
50 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
51 "finduuid=part uuid mmc 0:2 uuid\0" \
52 "mmcargs=setenv bootargs console=${console},${baudrate} " \
53 "root=PARTUUID=${uuid} rootwait rw\0" \
54 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
55 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
56 "mmcboot=echo Booting from mmc ...; " \
59 "if run loadfdt; then " \
60 "bootz ${loadaddr} - ${fdt_addr}; " \
62 "echo WARN: Cannot load the DT; " \
64 "netargs=setenv bootargs console=${console},${baudrate} " \
66 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
67 "netboot=echo Booting from net ...; " \
69 "if test ${ip_dyn} = yes; then " \
70 "setenv get_cmd dhcp; " \
72 "setenv get_cmd tftp; " \
74 "${get_cmd} ${image}; " \
75 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
76 "bootz ${loadaddr} - ${fdt_addr}; " \
78 "echo WARN: Cannot load the DT; " \
81 #define CONFIG_BOOTCOMMAND \
82 "if mmc rescan; then " \
83 "if run loadimage; then " \
85 "else run netboot; " \
87 "else run netboot; fi"
89 #define CONFIG_SYS_MEMTEST_START 0x80000000
90 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
92 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
93 #define CONFIG_SYS_HZ 1000
95 /* Physical Memory Map */
96 #define CONFIG_NR_DRAM_BANKS 1
97 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
99 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
100 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
101 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
103 #define CONFIG_SYS_INIT_SP_OFFSET \
104 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
105 #define CONFIG_SYS_INIT_SP_ADDR \
106 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
109 #define CONFIG_SYS_I2C
110 #define CONFIG_SYS_I2C_MXC
111 #define CONFIG_SYS_I2C_MXC_I2C1
112 #define CONFIG_SYS_I2C_MXC_I2C2
113 #define CONFIG_SYS_I2C_MXC_I2C3
114 #define CONFIG_SYS_I2C_MXC_I2C4
115 #define CONFIG_SYS_I2C_SPEED 100000
119 #define CONFIG_POWER_I2C
120 #define CONFIG_POWER_PFUZE3000
121 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
123 /* FLASH and environment organization */
124 #define CONFIG_ENV_SIZE SZ_8K
125 #define CONFIG_ENV_IS_IN_MMC
127 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
128 #define CONFIG_SYS_FSL_USDHC_NUM 2
130 #define CONFIG_SYS_MMC_ENV_DEV 0
131 #define CONFIG_SYS_MMC_ENV_PART 0
134 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
135 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
136 #define CONFIG_MXC_USB_FLAGS 0
137 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
139 #define CONFIG_IMX_THERMAL
141 #define CONFIG_USB_FUNCTION_MASS_STORAGE