3 * Ilko Iliev <iliev@ronetix.at>
4 * Asen Dimov <dimov@ronetix.at>
5 * Ronetix GmbH <www.ronetix.at>
7 * (C) Copyright 2007-2008
8 * Stelian Pop <stelian.pop@leadtechdesign.com>
9 * Lead Tech Design <www.leadtechdesign.com>
11 * Configuation settings for the PM9G45 board.
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
36 #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
37 #define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */
39 /* ARM asynchronous clock */
40 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
41 #define CONFIG_SYS_HZ 1000
43 #define CONFIG_ARCH_CPU_INIT
45 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
46 #define CONFIG_SETUP_MEMORY_TAGS 1
47 #define CONFIG_INITRD_TAG 1
49 #define CONFIG_SKIP_LOWLEVEL_INIT
50 #define CONFIG_SKIP_RELOCATE_UBOOT
55 #define CONFIG_AT91_GPIO 1
56 #define CONFIG_ATMEL_USART 1
57 #define CONFIG_USART3 1 /* USART 3 is DBGU */
59 #define CONFIG_SYS_USE_NANDFLASH 1
62 #define CONFIG_AT91_LED
63 #define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1 led */
64 #define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2 led */
66 #define CONFIG_BOOTDELAY 3
71 #define CONFIG_BOOTP_BOOTFILESIZE 1
72 #define CONFIG_BOOTP_BOOTPATH 1
73 #define CONFIG_BOOTP_GATEWAY 1
74 #define CONFIG_BOOTP_HOSTNAME 1
77 * Command line configuration.
79 #include <config_cmd_default.h>
80 #undef CONFIG_CMD_FPGA
81 #undef CONFIG_CMD_IMLS
83 #define CONFIG_CMD_PING 1
84 #define CONFIG_CMD_DHCP 1
85 #define CONFIG_CMD_NAND 1
86 #define CONFIG_CMD_USB 1
88 #define CONFIG_CMD_JFFS2 1
89 #define CONFIG_JFFS2_CMDLINE 1
90 #define CONFIG_JFFS2_NAND 1
91 #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */
92 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
93 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */
96 #define CONFIG_NR_DRAM_BANKS 1
97 #define PHYS_SDRAM 0x70000000
98 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
100 /* NOR flash, not available */
101 #define CONFIG_SYS_NO_FLASH 1
102 #undef CONFIG_CMD_FLASH
105 #ifdef CONFIG_CMD_NAND
106 #define CONFIG_NAND_MAX_CHIPS 1
107 #define CONFIG_NAND_ATMEL
108 #define CONFIG_SYS_MAX_NAND_DEVICE 1
109 #define CONFIG_SYS_NAND_BASE 0x40000000
110 #define CONFIG_SYS_NAND_DBW_8 1
111 /* our ALE is AD21 */
112 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
113 /* our CLE is AD22 */
114 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
115 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
116 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3
121 #define CONFIG_MACB 1
122 #define CONFIG_RMII 1
123 #define CONFIG_NET_MULTI 1
124 #define CONFIG_NET_RETRY_COUNT 20
125 #define CONFIG_RESET_PHY_R 1
128 #define CONFIG_USB_ATMEL
129 #define CONFIG_USB_OHCI_NEW 1
130 #define CONFIG_DOS_PARTITION 1
131 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
132 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */
133 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
134 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
135 #define CONFIG_USB_STORAGE 1
137 /* board specific(not enough SRAM) */
138 #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
140 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */
142 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
143 #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
145 /* bootstrap + u-boot + env + linux in nandflash */
146 #define CONFIG_ENV_IS_IN_NAND 1
147 #define CONFIG_ENV_OFFSET 0x60000
148 #define CONFIG_ENV_OFFSET_REDUND 0x80000
149 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
150 #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
151 #define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \
152 "console=ttyS0,115200 " \
153 "root=/dev/mtdblock4 " \
154 "mtdparts=atmel_nand:128k(bootstrap)ro," \
155 "256k(uboot)ro,1664k(env)," \
156 "2M(linux)ro,-(root) rw " \
159 #define CONFIG_BAUDRATE 115200
160 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
162 #define CONFIG_SYS_PROMPT "U-Boot> "
163 #define CONFIG_SYS_CBSIZE 256
164 #define CONFIG_SYS_MAXARGS 16
165 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
166 sizeof(CONFIG_SYS_PROMPT) + 16)
167 #define CONFIG_SYS_LONGHELP 1
168 #define CONFIG_CMDLINE_EDITING 1
169 #define CONFIG_AUTO_COMPLETE
170 #define CONFIG_SYS_HUSH_PARSER
171 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
174 * Size of malloc() pool
176 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
178 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
180 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
182 #ifdef CONFIG_USE_IRQ
183 #error CONFIG_USE_IRQ not supported