3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuation settings for the WindRiver PPMC8260 board.
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #define CONFIG_SYS_TEXT_BASE 0xfe000000
39 /*****************************************************************************
41 * These settings must match the way _your_ board is set up
43 *****************************************************************************/
45 /* What is the oscillator's (UX2) frequency in Hz? */
46 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
48 /*-----------------------------------------------------------------------
49 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
50 *-----------------------------------------------------------------------
51 * What should MODCK_H be? It is dependent on the oscillator
52 * frequency, MODCK[1-3], and desired CPM and core frequencies.
53 * Here are some example values (all frequencies are in MHz):
55 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
56 * ------- ---------- --- --- ---- ----- ----- -----
57 * 0x2 0x2 33 133 133 Close Open Close
58 * 0x2 0x3 33 133 166 Close Open Open
59 * 0x2 0x4 33 133 200 Open Close Close
60 * 0x2 0x5 33 133 233 Open Close Open
61 * 0x2 0x6 33 133 266 Open Open Close
63 * 0x5 0x5 66 133 133 Open Close Open
64 * 0x5 0x6 66 133 166 Open Open Close
65 * 0x5 0x7 66 133 200 Open Open Open
66 * 0x6 0x0 66 133 233 Close Close Close
67 * 0x6 0x1 66 133 266 Close Close Open
68 * 0x6 0x2 66 133 300 Close Open Close
70 #define CONFIG_SYS_PPMC_MODCK_H 0x05
72 /* Define this if you want to boot from 0x00000100. If you don't define
73 * this, you will need to program the bootloader to 0xfff00000, and
74 * get the hardware reset config words at 0xfe000000. The simplest
75 * way to do that is to program the bootloader at both addresses.
76 * It is suggested that you just let U-Boot live at 0x00000000.
78 #define CONFIG_SYS_PPMC_BOOT_LOW 1
80 /* What should the base address of the main FLASH be and how big is
81 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
82 * The main FLASH is whichever is connected to *CS0. U-Boot expects
83 * this to be the SIMM.
85 #define CONFIG_SYS_FLASH0_BASE 0xFE000000
86 #define CONFIG_SYS_FLASH0_SIZE 16
88 /* What should be the base address of the first SDRAM DIMM and how big is
91 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
92 #define CONFIG_SYS_SDRAM0_SIZE 128
94 /* What should be the base address of the second SDRAM DIMM and how big is
97 #define CONFIG_SYS_SDRAM1_BASE 0x08000000
98 #define CONFIG_SYS_SDRAM1_SIZE 128
100 /* What should be the base address of the on board SDRAM and how big is
103 #define CONFIG_SYS_SDRAM2_BASE 0x38000000
104 #define CONFIG_SYS_SDRAM2_SIZE 16
106 /* What should be the base address of the MAILBOX and how big is it
108 * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
110 #define CONFIG_SYS_MAILBOX_BASE 0x32000000
111 #define CONFIG_SYS_MAILBOX_SIZE 8192
113 /* What is the base address of the I/O select lines and how big is it
117 #define CONFIG_SYS_IOSELECT_BASE 0xE0000000
118 #define CONFIG_SYS_IOSELECT_SIZE 32
121 /* What should be the base address of the LEDs and switch S0?
122 * If you don't want them enabled, don't define this.
124 #define CONFIG_SYS_LED_BASE 0xF1000000
127 * PPMC8260 with 256 16 MB DIMM:
129 * 0x0000 0000 Exception Vector code, 8k
132 * 0x0000 2000 Free for Application Use
138 * 0x0FF5 FF30 Monitor Stack (Growing downward)
139 * Monitor Stack Buffer (0x80)
140 * 0x0FF5 FFB0 Board Info Data
141 * 0x0FF6 0000 Malloc Arena
142 * : CONFIG_ENV_SECT_SIZE, 256k
143 * : CONFIG_SYS_MALLOC_LEN, 128k
144 * 0x0FFC 0000 RAM Copy of Monitor Code
145 * : CONFIG_SYS_MONITOR_LEN, 256k
146 * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
151 * select serial console configuration
153 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
154 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
157 * if CONFIG_CONS_NONE is defined, then the serial console routines must
159 * The console can be on SMC1 or SMC2
161 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
162 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
163 #undef CONFIG_CONS_NONE /* define if console on neither */
164 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
167 * select ethernet configuration
169 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
170 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
173 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
174 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
177 #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
178 #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
179 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
180 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
181 #define CONFIG_MII /* MII PHY management */
182 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
184 * Port pins used for bit-banged MII communictions (if applicable).
186 #define MDIO_PORT 2 /* Port C */
187 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
188 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
189 #define MDC_DECLARE MDIO_DECLARE
191 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
192 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
193 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
195 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
196 else iop->pdat &= ~0x00400000
198 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
199 else iop->pdat &= ~0x00200000
201 #define MIIDELAY udelay(1)
204 /* Define this to reserve an entire FLASH sector (256 KB) for
205 * environment variables. Otherwise, the environment will be
206 * put in the same sector as U-Boot, and changing variables
207 * will erase U-Boot temporarily
209 #define CONFIG_ENV_IN_OWN_SECT 1
211 /* Define to allow the user to overwrite serial and ethaddr */
212 #define CONFIG_ENV_OVERWRITE
214 /* What should the console's baud rate be? */
215 #define CONFIG_BAUDRATE 9600
217 /* Ethernet MAC address */
219 #define CONFIG_ETHADDR 00:a0:1e:90:2b:00
221 /* Define this to set the last octet of the ethernet address
222 * from the DS0-DS7 switch and light the leds with the result
223 * The DS0-DS7 switch and the leds are backwards with respect
224 * to each other. DS7 is on the board edge side of both the
225 * led strip and the DS0-DS7 switch.
227 #define CONFIG_MISC_INIT_R
229 /* Set to a positive value to delay for running BOOTCOMMAND */
230 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
233 /* Be selective on what keys can delay or stop the autoboot process
236 # define CONFIG_AUTOBOOT_KEYED
237 # define CONFIG_AUTOBOOT_PROMPT \
238 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
239 # define CONFIG_AUTOBOOT_STOP_STR " "
240 # undef CONFIG_AUTOBOOT_DELAY_STR
241 # define DEBUG_BOOTKEYS 0
244 /* Define a command string that is automatically executed when no character
245 * is read on the console interface withing "Boot Delay" after reset.
247 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
248 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
250 #ifdef CONFIG_BOOT_ROOT_INITRD
251 #define CONFIG_BOOTCOMMAND \
255 "setenv bootargs root=/dev/ram0 rw " \
256 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
258 #endif /* CONFIG_BOOT_ROOT_INITRD */
260 #ifdef CONFIG_BOOT_ROOT_NFS
261 #define CONFIG_BOOTCOMMAND \
265 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
266 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
268 #endif /* CONFIG_BOOT_ROOT_NFS */
274 #define CONFIG_BOOTP_SUBNETMASK
275 #define CONFIG_BOOTP_GATEWAY
276 #define CONFIG_BOOTP_HOSTNAME
277 #define CONFIG_BOOTP_BOOTPATH
278 #define CONFIG_BOOTP_BOOTFILESIZE
279 #define CONFIG_BOOTP_DNS
282 /* undef this to save memory */
283 #define CONFIG_SYS_LONGHELP
285 /* Monitor Command Prompt */
286 #define CONFIG_SYS_PROMPT "=> "
290 * Command line configuration.
292 #include <config_cmd_default.h>
294 #define CONFIG_CMD_ELF
295 #define CONFIG_CMD_ASKENV
296 #define CONFIG_CMD_REGINFO
297 #define CONFIG_CMD_MEMTEST
298 #define CONFIG_CMD_MII
299 #define CONFIG_CMD_IMMAP
301 #undef CONFIG_CMD_KGDB
304 /* Where do the internal registers live? */
305 #define CONFIG_SYS_IMMR 0xf0000000
307 /*****************************************************************************
309 * You should not have to modify any of the following settings
311 *****************************************************************************/
313 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
314 #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
315 #define CONFIG_CPM2 1 /* Has a CPM2 */
318 * Miscellaneous configurable options
320 #if defined(CONFIG_CMD_KGDB)
321 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
323 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
326 /* Print Buffer Size */
327 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
329 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
331 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
333 #define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */
334 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
336 #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
337 /* the exception vector table */
338 /* to the end of the DRAM */
339 /* less monitor and malloc area */
340 #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
341 #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
342 + CONFIG_SYS_MALLOC_LEN \
343 + CONFIG_ENV_SECT_SIZE \
344 + CONFIG_SYS_STACK_USAGE )
346 #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
347 - CONFIG_SYS_MEM_END_USAGE )
349 /* valid baudrates */
350 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
353 * Low Level Configuration Settings
354 * (address mappings, register initial values, etc.)
355 * You should know what you are doing if you make changes here.
358 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
360 * Attention: This is board specific
364 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
367 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
369 * Attention: this is board-specific
372 * - Select bus for bd/buffers (see 28-13)
373 * - Enable Full Duplex in FSMR
375 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
376 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
377 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
378 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
379 #endif /* CONFIG_ETHER_INDEX */
381 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
382 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
383 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
384 #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
386 /*-----------------------------------------------------------------------
387 * Hard Reset Configuration Words
389 #if defined(CONFIG_SYS_PPMC_BOOT_LOW)
390 # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
392 # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0)
393 #endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
395 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
396 #define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
397 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
398 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
400 #define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \
404 CONFIG_SYS_PPMC_HRCW_IMMR | \
409 (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
410 CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
413 #define CONFIG_SYS_HRCW_SLAVE1 0
414 #define CONFIG_SYS_HRCW_SLAVE2 0
415 #define CONFIG_SYS_HRCW_SLAVE3 0
416 #define CONFIG_SYS_HRCW_SLAVE4 0
417 #define CONFIG_SYS_HRCW_SLAVE5 0
418 #define CONFIG_SYS_HRCW_SLAVE6 0
419 #define CONFIG_SYS_HRCW_SLAVE7 0
421 /*-----------------------------------------------------------------------
422 * Definitions for initial stack pointer and data area (in DPRAM)
424 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
425 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
426 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
427 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
428 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
430 /*-----------------------------------------------------------------------
431 * Start addresses for the final memory configuration
432 * (Set up by the startup code)
433 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
434 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
438 #ifndef CONFIG_SYS_MONITOR_BASE
439 #define CONFIG_SYS_MONITOR_BASE 0x0ff80000
442 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
443 # define CONFIG_SYS_RAMBOOT
446 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
447 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
450 * For booting Linux, the board info and command line data
451 * have to be in the first 8 MB of memory, since this is
452 * the maximum mapped by the Linux kernel during initialization.
454 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
456 /*-----------------------------------------------------------------------
457 * FLASH and environment organization
460 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
461 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
462 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
463 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
464 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
465 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
466 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
469 #ifndef CONFIG_SYS_RAMBOOT
471 # define CONFIG_ENV_IS_IN_FLASH 1
472 # ifdef CONFIG_ENV_IN_OWN_SECT
473 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
474 # define CONFIG_ENV_SECT_SIZE 0x40000
476 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
477 # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
478 # define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
479 # endif /* CONFIG_ENV_IN_OWN_SECT */
482 # define CONFIG_ENV_IS_IN_FLASH 1
483 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
484 #define CONFIG_ENV_SIZE 0x1000
485 # define CONFIG_ENV_SECT_SIZE 0x40000
486 #endif /* CONFIG_SYS_RAMBOOT */
488 /*-----------------------------------------------------------------------
489 * Cache Configuration
491 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
493 #if defined(CONFIG_CMD_KGDB)
494 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
497 /*-----------------------------------------------------------------------
498 * HIDx - Hardware Implementation-dependent Registers 2-11
499 *-----------------------------------------------------------------------
500 * HID0 also contains cache control - initially enable both caches and
501 * invalidate contents, then the final state leaves only the instruction
502 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
503 * but Soft reset does not.
505 * HID1 has only read-only information - nothing to set.
507 #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
514 #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
518 #define CONFIG_SYS_HID2 0
520 /*-----------------------------------------------------------------------
521 * RMR - Reset Mode Register
522 *-----------------------------------------------------------------------
524 #define CONFIG_SYS_RMR 0
526 /*-----------------------------------------------------------------------
527 * BCR - Bus Configuration 4-25
528 *-----------------------------------------------------------------------
530 #define CONFIG_SYS_BCR (BCR_EBM |\
533 /*-----------------------------------------------------------------------
534 * SIUMCR - SIU Module Configuration 4-31
535 * Ref Section 4.3.2.6 page 4-31
536 *-----------------------------------------------------------------------
539 #define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\
549 /*-----------------------------------------------------------------------
550 * SYPCR - System Protection Control 11-9
551 * SYPCR can only be written once after reset!
552 *-----------------------------------------------------------------------
553 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
555 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
562 /*-----------------------------------------------------------------------
563 * TMCNTSC - Time Counter Status and Control 4-40
564 *-----------------------------------------------------------------------
565 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
566 * and enable Time Counter
568 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
573 /*-----------------------------------------------------------------------
574 * PISCR - Periodic Interrupt Status and Control 4-42
575 *-----------------------------------------------------------------------
576 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
579 #define CONFIG_SYS_PISCR (PISCR_PS |\
583 /*-----------------------------------------------------------------------
584 * SCCR - System Clock Control 9-8
585 *-----------------------------------------------------------------------
587 #define CONFIG_SYS_SCCR 0
589 /*-----------------------------------------------------------------------
590 * RCCR - RISC Controller Configuration 13-7
591 *-----------------------------------------------------------------------
593 #define CONFIG_SYS_RCCR 0
596 * Initialize Memory Controller:
598 * Bank Bus Machine PortSz Device
599 * ---- --- ------- ------ ------
600 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
602 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
603 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
604 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
605 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
606 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
607 * 7 60x GPCM 8 bit LEDs, switches
609 * (*) This configuration requires the PPMC8260 be configured
610 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
611 * the on board FLASH. In other words, JP24 should have
612 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
616 /*-----------------------------------------------------------------------
617 * BR0,BR1 - Base Register
618 * Ref: Section 10.3.1 on page 10-14
619 * OR0,OR1 - Option Register
620 * Ref: Section 10.3.2 on page 10-18
621 *-----------------------------------------------------------------------
624 /* Bank 0,1 - FLASH SIMM
626 * This expects the FLASH SIMM to be connected to *CS0
627 * It consists of 4 AM29F080B parts.
629 * Note: For the 4 MB SIMM, *CS1 is unused.
632 /* BR0 is configured as follows:
634 * - Base address of 0xFE000000
636 * - Data errors checking is disabled
637 * - Read and write access
639 * - Access are handled by the memory controller according to MSEL
640 * - Not used for atomic operations
641 * - No data pipelining is done
644 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
649 /* OR0 is configured as follows:
652 * - *BCTL0 is asserted upon access to the current memory bank
653 * - *CW / *WE are negated a quarter of a clock earlier
654 * - *CS is output at the same time as the address lines
655 * - Uses a clock cycle length of 5
656 * - *PSDVAL is generated internally by the memory controller
657 * unless *GTA is asserted earlier externally.
658 * - Relaxed timing is generated by the GPCM for accesses
659 * initiated to this memory region.
660 * - One idle clock is inserted between a read access from the
661 * current bank and the next access.
663 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
670 /*-----------------------------------------------------------------------
671 * BR2,BR3 - Base Register
672 * Ref: Section 10.3.1 on page 10-14
673 * OR2,OR3 - Option Register
674 * Ref: Section 10.3.2 on page 10-16
675 *-----------------------------------------------------------------------
679 * Bank 2,3 - 128 MB SDRAM DIMM
682 /* With a 128 MB DIMM, the BR2 is configured as follows:
684 * - Base address of 0x00000000/0x08000000
685 * - 64 bit port size (60x bus only)
686 * - Data errors checking is disabled
687 * - Read and write access
689 * - Access are handled by the memory controller according to MSEL
690 * - Not used for atomic operations
691 * - No data pipelining is done
694 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
699 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
704 /* With a 128 MB DIMM, the OR2 is configured as follows:
707 * - 4 internal banks per device
708 * - Row start address bit is A8 with PSDMR[PBI] = 0
709 * - 13 row address lines
710 * - Back-to-back page mode
711 * - Internal bank interleaving within save device enabled
714 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
716 ORxS_ROWST_PBI0_A7 |\
719 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
721 ORxS_ROWST_PBI0_A7 |\
725 /*-----------------------------------------------------------------------
726 * PSDMR - 60x Bus SDRAM Mode Register
727 * Ref: Section 10.3.3 on page 10-21
728 *-----------------------------------------------------------------------
731 /* With a 128 MB DIMM, the PSDMR is configured as follows:
733 * - Page Based Interleaving,
736 * - Address Multiplexing where A5 is output on A14 pin
737 * (A6 on A15, and so on),
738 * - use address pins A13-A15 as bank select,
739 * - A9 is output on SDA10 during an ACTIVATE command,
740 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
741 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
743 * - earliest timing for READ/WRITE command after ACTIVATE command is
745 * - earliest timing for PRECHARGE after last data was read is 1 clock,
746 * - earliest timing for PRECHARGE after last data was written is 1 clock,
747 * - External Address Multiplexing enabled
748 * - CAS Latency is 2.
750 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
751 PSDMR_SDAM_A14_IS_A5 |\
752 PSDMR_BSMA_A13_A15 |\
753 PSDMR_SDA10_PBI0_A9 |\
763 #define CONFIG_SYS_PSRT 0x0e
764 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
767 /*-----------------------------------------------------------------------
768 * BR4 - Base Register
769 * Ref: Section 10.3.1 on page 10-14
770 * OR4 - Option Register
771 * Ref: Section 10.3.2 on page 10-16
772 *-----------------------------------------------------------------------
776 * Bank 4 - On board SDRAM
779 /* With 16 MB of onboard SDRAM BR4 is configured as follows
781 * - Base address 0x38000000
783 * - Data error checking disabled
784 * - Read/Write access
786 * - Not used for atomic operations
787 * - No data pipelining is done
792 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
799 * With 16MB SDRAM, OR4 is configured as follows
800 * - 4 internal banks per device
801 * - Row start address bit is A10 with LSDMR[PBI] = 0
802 * - 12 row address lines
803 * - Back-to-back page mode
804 * - Internal bank interleaving within save device enabled
807 #define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\
809 ORxS_ROWST_PBI0_A10 |\
813 /*-----------------------------------------------------------------------
814 * LSDMR - Local Bus SDRAM Mode Register
815 * Ref: Section 10.3.4 on page 10-24
816 *-----------------------------------------------------------------------
819 /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
821 * - Page Based Interleaving,
824 * - Address Multiplexing where A5 is output on A13 pin
825 * (A6 on A15, and so on),
826 * - use address pins A15-A17 as bank select,
827 * - A11 is output on SDA10 during an ACTIVATE command,
828 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
829 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
831 * - earliest timing for READ/WRITE command after ACTIVATE command is
833 * - SDRAM burst length is 8
834 * - earliest timing for PRECHARGE after last data was read is 1 clock,
835 * - earliest timing for PRECHARGE after last data was written is 1 clock,
836 * - External Address Multiplexing disabled
837 * - CAS Latency is 2.
839 #define CONFIG_SYS_LSDMR (PSDMR_RFEN |\
840 PSDMR_SDAM_A13_IS_A5 |\
841 PSDMR_BSMA_A15_A17 |\
842 PSDMR_SDA10_PBI0_A11 |\
851 #define CONFIG_SYS_LSRT 0x0e
853 /*-----------------------------------------------------------------------
854 * BR5 - Base Register
855 * Ref: Section 10.3.1 on page 10-14
856 * OR5 - Option Register
857 * Ref: Section 10.3.2 on page 10-16
858 *-----------------------------------------------------------------------
862 * Bank 5 EEProm and Mailbox
864 * The EEPROM and mailbox live on the same chip select.
865 * the eeprom is selected if the MSb of the address is set and the mailbox is
866 * selected if the MSb of the address is clear.
870 /* BR5 is configured as follows:
872 * - Base address of 0x32000000/0xF2000000
874 * - Data error checking disabled
875 * - Read/Write access
878 * - No data pipelining is done
882 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
887 /* OR5 is configured as follows
888 * - buffer control enabled
889 * - chip select negated normally
890 * - CS output 1/2 clock after address
892 * - *PSDVAL is generated internally by the memory controller
893 * unless *GTA is asserted earlier externally.
894 * - Relaxed timing is generated by the GPCM for accesses
895 * initiated to this memory region.
896 * - One idle clock is inserted between a read access from the
897 * current bank and the next access.
900 #define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
906 /*-----------------------------------------------------------------------
907 * BR6 - Base Register
908 * Ref: Section 10.3.1 on page 10-14
909 * OR6 - Option Register
910 * Ref: Section 10.3.2 on page 10-18
911 *-----------------------------------------------------------------------
914 /* Bank 6 - I/O select
918 /* BR6 is configured as follows:
920 * - Base address of 0xE0000000
922 * - Data errors checking is disabled
923 * - Read and write access
925 * - Access are handled by the memory controller according to MSEL
926 * - Not used for atomic operations
927 * - No data pipelining is done
930 #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
935 /* OR6 is configured as follows
936 * - buffer control enabled
937 * - chip select negated normally
938 * - CS output 1/2 clock after address
940 * - *PSDVAL is generated internally by the memory controller
941 * unless *GTA is asserted earlier externally.
942 * - Relaxed timing is generated by the GPCM for accesses
943 * initiated to this memory region.
944 * - One idle clock is inserted between a read access from the
945 * current bank and the next access.
948 #define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
955 /*-----------------------------------------------------------------------
956 * BR7 - Base Register
957 * Ref: Section 10.3.1 on page 10-14
958 * OR7 - Option Register
959 * Ref: Section 10.3.2 on page 10-18
960 *-----------------------------------------------------------------------
963 /* Bank 7 - LEDs and switches
965 * LEDs are at 0x00001 (write only)
966 * switches are at 0x00001 (read only)
968 #ifdef CONFIG_SYS_LED_BASE
970 /* BR7 is configured as follows:
972 * - Base address of 0xA0000000
974 * - Data errors checking is disabled
975 * - Read and write access
977 * - Access are handled by the memory controller according to MSEL
978 * - Not used for atomic operations
979 * - No data pipelining is done
982 #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\
988 /* OR7 is configured as follows:
991 * - *BCTL0 is asserted upon access to the current memory bank
992 * - *CW / *WE are negated a quarter of a clock earlier
993 * - *CS is output at the same time as the address lines
994 * - Uses a clock cycle length of 15
995 * - *PSDVAL is generated internally by the memory controller
996 * unless *GTA is asserted earlier externally.
997 * - Relaxed timing is generated by the GPCM for accesses
998 * initiated to this memory region.
999 * - One idle clock is inserted between a read access from the
1000 * current bank and the next access.
1002 #define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\
1008 #endif /* CONFIG_SYS_LED_BASE */
1009 #endif /* __CONFIG_H */