2 * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 3 of the License, or (at your option) any later version.
10 #ifndef __CONFIG_QI_LB60_H
11 #define __CONFIG_QI_LB60_H
13 #define CONFIG_MIPS32 /* MIPS32 CPU core */
14 #define CONFIG_JZSOC /* Jz SoC */
15 #define CONFIG_JZ4740 /* Jz4740 SoC */
16 #define CONFIG_NAND_JZ4740
18 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
19 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
20 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
21 #define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
23 #define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
24 #define CONFIG_BAUDRATE 57600
26 #define CONFIG_SKIP_LOWLEVEL_INIT
27 #define CONFIG_BOARD_EARLY_INIT_F
28 #define CONFIG_SYS_NO_FLASH
29 #define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
30 #define CONFIG_ENV_OVERWRITE
32 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
33 #define CONFIG_BOOTDELAY 0
34 #define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
35 #define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
38 * Command line configuration.
40 #define CONFIG_CMD_BOOTD /* bootd */
41 #define CONFIG_CMD_CONSOLE /* coninfo */
42 #define CONFIG_CMD_ECHO /* echo arguments */
44 #define CONFIG_CMD_LOADB /* loadb */
45 #define CONFIG_CMD_LOADS /* loads */
46 #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
47 #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
48 #define CONFIG_CMD_RUN /* run command in env variable */
49 #define CONFIG_CMD_SAVEENV /* saveenv */
50 #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
51 #define CONFIG_CMD_SOURCE /* "source" command support */
52 #define CONFIG_CMD_NAND
55 * Serial download configuration
57 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60 * Miscellaneous configurable options
62 #define CONFIG_SYS_MAXARGS 16
63 #define CONFIG_SYS_LONGHELP
64 #define CONFIG_SYS_PROMPT "NanoNote# "
65 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
66 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
68 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
69 #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
71 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
72 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
73 #define CONFIG_SYS_LOAD_ADDR 0x80600000
74 #define CONFIG_SYS_MEMTEST_START 0x80100000
75 #define CONFIG_SYS_MEMTEST_END 0x80800000
80 #define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
82 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
84 * if board nand flash is 1GB, set to 1
85 * if board nand flash is 2GB, set to 2
86 * for change the PAGE_SIZE and BLOCK_SIZE
87 * will delete when there is no 1GB flash
89 #define NANONOTE_NAND_SIZE 2
91 #define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
92 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
93 /* nand bad block was marked at this page in a block, start from 0 */
94 #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
95 #define CONFIG_SYS_NAND_PAGE_COUNT 128
96 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
97 /* ECC offset position in oob area, default value is 6 if it isn't defined */
98 #define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
99 #define CONFIG_SYS_NAND_ECCSIZE 512
100 #define CONFIG_SYS_NAND_ECCBYTES 9
101 #define CONFIG_SYS_NAND_ECCPOS \
102 {12, 13, 14, 15, 16, 17, 18, 19,\
103 20, 21, 22, 23, 24, 25, 26, 27, \
104 28, 29, 30, 31, 32, 33, 34, 35, \
105 36, 37, 38, 39, 40, 41, 42, 43, \
106 44, 45, 46, 47, 48, 49, 50, 51, \
107 52, 53, 54, 55, 56, 57, 58, 59, \
108 60, 61, 62, 63, 64, 65, 66, 67, \
109 68, 69, 70, 71, 72, 73, 74, 75, \
110 76, 77, 78, 79, 80, 81, 82, 83}
112 #define CONFIG_SYS_NAND_OOBSIZE 128
113 #define CONFIG_SYS_NAND_BASE 0xB8000000
114 #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
115 #define CONFIG_SYS_MAX_NAND_DEVICE 1
116 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
117 #define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
120 * IPL (Initial Program Loader, integrated inside CPU)
121 * Will load first 8k from NAND (SPL) into cache and execute it from there.
123 * SPL (Secondary Program Loader)
124 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
125 * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
126 * controller and the NAND controller so that the special U-Boot image can be
127 * loaded from NAND to SDRAM.
130 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
131 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
134 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
135 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
136 /* Start NUB from this addr*/
139 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
141 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
142 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
144 #define CONFIG_ENV_SIZE (4 << 10)
145 #define CONFIG_ENV_OFFSET \
146 (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
147 #define CONFIG_ENV_OFFSET_REDUND \
148 (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
150 #define CONFIG_SYS_TEXT_BASE 0x80100000
151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
156 #define CONFIG_NR_DRAM_BANKS 1
159 * Cache Configuration
161 #define CONFIG_SYS_DCACHE_SIZE 16384
162 #define CONFIG_SYS_ICACHE_SIZE 16384
163 #define CONFIG_SYS_CACHELINE_SIZE 32
168 #define GPIO_LCD_CS (2 * 32 + 21)
169 #define GPIO_AMP_EN (3 * 32 + 4)
171 #define GPIO_SDPW_EN (3 * 32 + 2)
172 #define GPIO_SD_DETECT (3 * 32 + 0)
174 #define GPIO_BUZZ_PWM (3 * 32 + 27)
175 #define GPIO_USB_DETECT (3 * 32 + 28)
177 #define GPIO_AUDIO_POP (1 * 32 + 29)
178 #define GPIO_COB_TEST (1 * 32 + 30)
180 #define GPIO_KEYOUT_BASE (2 * 32 + 10)
181 #define GPIO_KEYIN_BASE (3 * 32 + 18)
182 #define GPIO_KEYIN_8 (3 * 32 + 26)
184 #define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
185 #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
187 #define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
188 #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
189 #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
191 /* SDRAM paramters */
192 #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
193 #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
194 #define SDRAM_ROW 13 /* Row address: 11 to 13 */
195 #define SDRAM_COL 9 /* Column address: 8 to 12 */
196 #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
198 /* SDRAM Timings, unit: ns */
199 #define SDRAM_TRAS 45 /* RAS# Active Time */
200 #define SDRAM_RCD 20 /* RAS# to CAS# Delay */
201 #define SDRAM_TPC 20 /* RAS# Precharge Time */
202 #define SDRAM_TRWL 7 /* Write Latency Time */
203 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */