2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
26 * changes for 16M board
33 * High Level Configuration Options
38 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39 #define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
40 #define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43 #undef CONFIG_8xx_CONS_SMC2
44 #undef CONFIG_8xx_CONS_NONE
45 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
47 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
49 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52 /* default developmenmt environment */
54 #define CONFIG_ETHADDR 00:0B:17:00:00:00
56 #define CONFIG_IPADDR 10.10.69.10
57 #define CONFIG_SERVERIP 10.10.69.49
58 #define CONFIG_NETMASK 255.255.255.0
59 #define CONFIG_HOSTNAME QUANTUM
60 #define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
62 #define CONFIG_BOOTARGS "root=/dev/ram rw"
64 #define CONFIG_BOOTCOMMAND "bootm ff000000"
66 #define CONFIG_EXTRA_ENV_SETTINGS \
68 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
69 "ramargs=setenv bootargs root=/dev/ram rw\0" \
70 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
73 * Select the more full-featured memory test (Barr embedded systems)
75 #define CFG_ALT_MEMTEST
77 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
81 /* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
82 #define CONFIG_RTC_M48T35A 1
85 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
87 #undef CONFIG_WATCHDOG
91 #define CFG_NVRAM_BASE_ADDR 0xFA000000
92 #define CFG_NVRAM_SIZE 2048
96 * Command line configuration.
98 #include <config_cmd_default.h>
100 #define CONFIG_CMD_DATE
101 #define CONFIG_CMD_DHCP
102 #define CONFIG_CMD_NFS
103 #define CONFIG_CMD_PING
104 #define CONFIG_CMD_REGINFO
105 #define CONFIG_CMD_SNTP
108 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
110 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
111 #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
112 #define CONFIG_AUTOBOOT_DELAY_STR "system"
114 * Miscellaneous configurable options
116 #define CFG_LONGHELP /* undef to save memory */
117 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
118 #if defined(CONFIG_CMD_KGDB)
119 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
121 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
123 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
124 #define CFG_MAXARGS 16 /* max number of command args */
125 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
127 #define CFG_MEMTEST_START 0x00040000 /* memtest works on */
128 #define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
130 #define CFG_LOAD_ADDR 0x100000 /* default load address */
132 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
134 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
141 /*-----------------------------------------------------------------------
142 * Internal Memory Mapped Register
144 #define CFG_IMMR 0xFA200000
146 /*-----------------------------------------------------------------------
147 * Definitions for initial stack pointer and data area (in DPRAM)
149 #define CFG_INIT_RAM_ADDR CFG_IMMR
150 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
151 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
152 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
153 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
155 /*-----------------------------------------------------------------------
156 * Start addresses for the final memory configuration
157 * (Set up by the startup code)
158 * Please note that CFG_SDRAM_BASE _must_ start at 0
160 #define CFG_SDRAM_BASE 0x00000000
161 #define CFG_FLASH_BASE 0xFF000000
164 #define CFG_FLASH_CFI_DRIVER
166 #undef CFG_FLASH_CFI_DRIVER
170 #ifdef CFG_FLASH_CFI_DRIVER
171 #define CFG_FLASH_CFI 1
172 #undef CFG_FLASH_USE_BUFFER_WRITE
173 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
176 /*%%% #define CFG_FLASH_BASE 0xFFF00000 */
177 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
178 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
180 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
182 #define CFG_MONITOR_BASE 0xFFF00000
183 /*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
184 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
187 * For booting Linux, the board info and command line data
188 * have to be in the first 8 MB of memory, since this is
189 * the maximum mapped by the Linux kernel during initialization.
191 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
193 /*-----------------------------------------------------------------------
196 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
197 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
199 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
200 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
202 #define CFG_ENV_IS_IN_FLASH 1
203 #define CFG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/
204 #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
205 #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
206 #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
208 /* Address and size of Redundant Environment Sector */
209 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
210 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
213 #define CONFIG_MISC_INIT_R
214 #define CFG_FPGA_SPARTAN2
215 #define CFG_FPGA_PROG_FEEDBACK
218 /*-----------------------------------------------------------------------
221 #define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
223 /*-----------------------------------------------------------------------
224 * Cache Configuration
226 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
227 #if defined(CONFIG_CMD_KGDB)
228 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
231 /*-----------------------------------------------------------------------
232 * SYPCR - System Protection Control 11-9
233 * SYPCR can only be written once after reset!
234 *-----------------------------------------------------------------------
235 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
237 #if defined(CONFIG_WATCHDOG)
238 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
239 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
241 #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
244 /*-----------------------------------------------------------------------
245 * SIUMCR - SIU Module Configuration 11-6
246 *-----------------------------------------------------------------------
247 * PCMCIA config., multi-function pin tri-state
249 #define CFG_SIUMCR (SIUMCR_MLRC10)
251 /*-----------------------------------------------------------------------
252 * TBSCR - Time Base Status and Control 11-26
253 *-----------------------------------------------------------------------
254 * Clear Reference Interrupt Status, Timebase freezing enabled
256 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
258 /*-----------------------------------------------------------------------
259 * RTCSC - Real-Time Clock Status and Control Register 11-27
260 *-----------------------------------------------------------------------
262 /*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
263 #define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
265 /*-----------------------------------------------------------------------
266 * PISCR - Periodic Interrupt Status and Control 11-31
267 *-----------------------------------------------------------------------
268 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
270 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
272 /*-----------------------------------------------------------------------
273 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
274 *-----------------------------------------------------------------------
275 * Reset PLL lock status sticky bit, timer expired status bit and timer
276 * interrupt status bit
278 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
280 /* up to 50 MHz we use a 1:1 clock */
281 #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
283 /*-----------------------------------------------------------------------
284 * SCCR - System Clock and reset Control Register 15-27
285 *-----------------------------------------------------------------------
286 * Set clock output, timebase and RTC source and divider,
287 * power management and some other internal clocks
289 #define SCCR_MASK SCCR_EBDF00
290 /* up to 50 MHz we use a 1:1 clock */
291 #define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
293 /*-----------------------------------------------------------------------
295 *-----------------------------------------------------------------------
298 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
299 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
300 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
301 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
302 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
303 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
304 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
305 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
307 /*-----------------------------------------------------------------------
308 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
309 *-----------------------------------------------------------------------
312 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
314 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
315 #undef CONFIG_IDE_LED /* LED for ide not supported */
316 #undef CONFIG_IDE_RESET /* reset for ide not supported */
318 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
319 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
321 #define CFG_ATA_IDE0_OFFSET 0x0000
323 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
325 /* Offset for data I/O */
326 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
328 /* Offset for normal register accesses */
329 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
331 /* Offset for alternate registers */
332 #define CFG_ATA_ALT_OFFSET 0x0100
334 /*-----------------------------------------------------------------------
336 *-----------------------------------------------------------------------
339 /*#define CFG_DER 0x2002000F*/
343 * Init Memory Controller:
345 * BR0 and OR0 (FLASH)
348 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
349 #define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
351 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
352 #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
354 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
355 #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
358 * BR1 and OR1 (SDRAM)
361 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
362 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
364 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
365 #define CFG_OR_TIMING_SDRAM 0x00000E00
367 #define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
368 #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
370 /* RPXLITE mem setting */
371 #define CFG_BR3_PRELIM 0xFA400001 /* FPGA */
372 #define CFG_OR3_PRELIM 0xFFFF8910
374 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
375 #define CFG_OR4_PRELIM 0xFFFE0970
378 * Memory Periodic Timer Prescaler
381 /* periodic timer for refresh */
382 #define CFG_MAMR_PTA 20
385 * Refresh clock Prescalar
387 #define CFG_MPTPR MPTPR_PTP_DIV2
390 * MAMR settings for SDRAM
394 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
395 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
396 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
399 * Internal Definitions
403 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
404 #define BOOTFLAG_WARM 0x02 /* Software reboot */
409 * Board Status and Control Registers
413 #define BCSR0 0xFA400000
414 #define BCSR1 0xFA400001
415 #define BCSR2 0xFA400002
416 #define BCSR3 0xFA400003
418 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
419 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
420 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
421 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
422 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
423 #define BCSR0_COLTEST 0x20
424 #define BCSR0_ETHLPBK 0x40
425 #define BCSR0_ETHEN 0x80
427 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
428 #define BCSR1_PCVCTL6 0x02
429 #define BCSR1_PCVCTL5 0x04
430 #define BCSR1_PCVCTL4 0x08
431 #define BCSR1_IPB5SEL 0x10
433 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
434 #define BCSR2_ENUSBCLK 0x10
435 #define BCSR2_USBPWREN 0x20
436 #define BCSR2_USBSPD 0x40
437 #define BCSR2_USBSUSP 0x80
439 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
440 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
441 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
442 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
443 #define BCSR3_D27 0x10 /* Dip Switch settings */
444 #define BCSR3_D26 0x20
445 #define BCSR3_D25 0x40
446 #define BCSR3_D24 0x80
448 #endif /* __CONFIG_H */