2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
10 * changes for 16M board
17 * High Level Configuration Options
22 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
23 #define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
24 #define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
28 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29 #undef CONFIG_8xx_CONS_SMC2
30 #undef CONFIG_8xx_CONS_NONE
31 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
33 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
35 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
38 /* default developmenmt environment */
40 #define CONFIG_ETHADDR 00:0B:17:00:00:00
42 #define CONFIG_IPADDR 10.10.69.10
43 #define CONFIG_SERVERIP 10.10.69.49
44 #define CONFIG_NETMASK 255.255.255.0
45 #define CONFIG_HOSTNAME QUANTUM
46 #define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"
48 #define CONFIG_BOOTARGS "root=/dev/ram rw"
50 #define CONFIG_BOOTCOMMAND "bootm ff000000"
52 #define CONFIG_EXTRA_ENV_SETTINGS \
54 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
55 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
59 * Select the more full-featured memory test (Barr embedded systems)
61 #define CONFIG_SYS_ALT_MEMTEST
63 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
64 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
67 /* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
68 #define CONFIG_RTC_M48T35A 1
71 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
73 #undef CONFIG_WATCHDOG
77 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
78 #define CONFIG_SYS_NVRAM_SIZE 2048
82 * Command line configuration.
84 #include <config_cmd_default.h>
86 #define CONFIG_CMD_DATE
87 #define CONFIG_CMD_DHCP
88 #define CONFIG_CMD_NFS
89 #define CONFIG_CMD_PING
90 #define CONFIG_CMD_REGINFO
91 #define CONFIG_CMD_SNTP
97 #define CONFIG_BOOTP_SUBNETMASK
98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME
100 #define CONFIG_BOOTP_BOOTPATH
101 #define CONFIG_BOOTP_BOOTFILESIZE
104 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
105 #define CONFIG_AUTOBOOT_PROMPT \
106 "\nEnter password - autoboot in %d sec...\n", bootdelay
107 #define CONFIG_AUTOBOOT_DELAY_STR "system"
109 * Miscellaneous configurable options
111 #define CONFIG_SYS_LONGHELP /* undef to save memory */
112 #if defined(CONFIG_CMD_KGDB)
113 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
115 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
118 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
119 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
121 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */
122 #define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
124 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
126 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
129 * Low Level Configuration Settings
130 * (address mappings, register initial values, etc.)
131 * You should know what you are doing if you make changes here.
133 /*-----------------------------------------------------------------------
134 * Internal Memory Mapped Register
136 #define CONFIG_SYS_IMMR 0xFA200000
138 /*-----------------------------------------------------------------------
139 * Definitions for initial stack pointer and data area (in DPRAM)
141 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
142 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
143 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
144 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
146 /*-----------------------------------------------------------------------
147 * Start addresses for the final memory configuration
148 * (Set up by the startup code)
149 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
151 #define CONFIG_SYS_SDRAM_BASE 0x00000000
152 #define CONFIG_SYS_FLASH_BASE 0xFF000000
155 #define CONFIG_FLASH_CFI_DRIVER
157 #undef CONFIG_FLASH_CFI_DRIVER
161 #ifdef CONFIG_FLASH_CFI_DRIVER
162 #define CONFIG_SYS_FLASH_CFI 1
163 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
164 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
167 /*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */
168 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
169 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
171 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
173 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
174 /*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
175 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
178 * For booting Linux, the board info and command line data
179 * have to be in the first 8 MB of memory, since this is
180 * the maximum mapped by the Linux kernel during initialization.
182 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
184 /*-----------------------------------------------------------------------
187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
190 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
193 #define CONFIG_ENV_IS_IN_FLASH 1
194 #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/
195 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
196 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
197 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
199 /* Address and size of Redundant Environment Sector */
200 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
201 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
204 #define CONFIG_MISC_INIT_R
205 #define CONFIG_SYS_FPGA_SPARTAN2
206 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
209 /*-----------------------------------------------------------------------
212 #define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
214 /*-----------------------------------------------------------------------
215 * Cache Configuration
217 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
218 #if defined(CONFIG_CMD_KGDB)
219 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
222 /*-----------------------------------------------------------------------
223 * SYPCR - System Protection Control 11-9
224 * SYPCR can only be written once after reset!
225 *-----------------------------------------------------------------------
226 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
228 #if defined(CONFIG_WATCHDOG)
229 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
230 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
232 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
235 /*-----------------------------------------------------------------------
236 * SIUMCR - SIU Module Configuration 11-6
237 *-----------------------------------------------------------------------
238 * PCMCIA config., multi-function pin tri-state
240 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
242 /*-----------------------------------------------------------------------
243 * TBSCR - Time Base Status and Control 11-26
244 *-----------------------------------------------------------------------
245 * Clear Reference Interrupt Status, Timebase freezing enabled
247 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
249 /*-----------------------------------------------------------------------
250 * RTCSC - Real-Time Clock Status and Control Register 11-27
251 *-----------------------------------------------------------------------
253 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
254 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
256 /*-----------------------------------------------------------------------
257 * PISCR - Periodic Interrupt Status and Control 11-31
258 *-----------------------------------------------------------------------
259 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
261 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
263 /*-----------------------------------------------------------------------
264 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
265 *-----------------------------------------------------------------------
266 * Reset PLL lock status sticky bit, timer expired status bit and timer
267 * interrupt status bit
269 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
271 /* up to 50 MHz we use a 1:1 clock */
272 #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
274 /*-----------------------------------------------------------------------
275 * SCCR - System Clock and reset Control Register 15-27
276 *-----------------------------------------------------------------------
277 * Set clock output, timebase and RTC source and divider,
278 * power management and some other internal clocks
280 #define SCCR_MASK SCCR_EBDF00
281 /* up to 50 MHz we use a 1:1 clock */
282 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
284 /*-----------------------------------------------------------------------
286 *-----------------------------------------------------------------------
289 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
290 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
291 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
292 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
293 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
294 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
295 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
296 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
298 /*-----------------------------------------------------------------------
299 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
300 *-----------------------------------------------------------------------
303 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
304 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
306 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
307 #undef CONFIG_IDE_LED /* LED for ide not supported */
308 #undef CONFIG_IDE_RESET /* reset for ide not supported */
310 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
311 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
313 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
315 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
317 /* Offset for data I/O */
318 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
320 /* Offset for normal register accesses */
321 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
323 /* Offset for alternate registers */
324 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
326 /*-----------------------------------------------------------------------
328 *-----------------------------------------------------------------------
331 /*#define CONFIG_SYS_DER 0x2002000F*/
332 #define CONFIG_SYS_DER 0
335 * Init Memory Controller:
337 * BR0 and OR0 (FLASH)
340 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
341 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
343 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
344 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
346 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
347 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
350 * BR1 and OR1 (SDRAM)
353 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
354 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
356 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
357 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
359 #define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
360 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
362 /* RPXLITE mem setting */
363 #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */
364 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
366 #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
367 #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
370 * Memory Periodic Timer Prescaler
373 /* periodic timer for refresh */
374 #define CONFIG_SYS_MAMR_PTA 20
377 * Refresh clock Prescalar
379 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
382 * MAMR settings for SDRAM
386 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
387 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
388 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
393 * Board Status and Control Registers
397 #define BCSR0 0xFA400000
398 #define BCSR1 0xFA400001
399 #define BCSR2 0xFA400002
400 #define BCSR3 0xFA400003
402 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
403 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
404 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
405 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
406 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
407 #define BCSR0_COLTEST 0x20
408 #define BCSR0_ETHLPBK 0x40
409 #define BCSR0_ETHEN 0x80
411 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
412 #define BCSR1_PCVCTL6 0x02
413 #define BCSR1_PCVCTL5 0x04
414 #define BCSR1_PCVCTL4 0x08
415 #define BCSR1_IPB5SEL 0x10
417 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
418 #define BCSR2_ENUSBCLK 0x10
419 #define BCSR2_USBPWREN 0x20
420 #define BCSR2_USBSPD 0x40
421 #define BCSR2_USBSUSP 0x80
423 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
424 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
425 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
426 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
427 #define BCSR3_D27 0x10 /* Dip Switch settings */
428 #define BCSR3_D26 0x20
429 #define BCSR3_D25 0x40
430 #define BCSR3_D24 0x80
432 #endif /* __CONFIG_H */