4 #define CONFIG_CPU_SH7751 1
5 #define CONFIG_CPU_SH_TYPE_R 1
6 #define CONFIG_R2DPLUS 1
7 #define __LITTLE_ENDIAN__ 1
9 #define CONFIG_DISPLAY_BOARDINFO
12 #define CONFIG_CONS_SCIF1 1
14 #define CONFIG_ENV_OVERWRITE 1
17 #define CONFIG_SYS_SDRAM_BASE 0x8C000000
18 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
20 #define CONFIG_SYS_TEXT_BASE 0x8FE00000
21 #define CONFIG_SYS_LONGHELP
22 #define CONFIG_SYS_PBSIZE 256
24 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
25 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
28 /* Address of u-boot image in Flash */
29 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
30 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
31 /* Size of DRAM reserved for malloc() use */
32 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
33 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
36 * NOR Flash ( Spantion S29GL256P )
38 #define CONFIG_SYS_FLASH_CFI
39 #define CONFIG_FLASH_CFI_DRIVER
40 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
41 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
42 #define CONFIG_SYS_MAX_FLASH_SECT 256
43 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
45 #define CONFIG_ENV_SECT_SIZE 0x40000
46 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
47 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
50 * SuperH Clock setting
52 #define CONFIG_SYS_CLK_FREQ 60000000
53 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
54 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
55 #define CONFIG_SYS_TMU_CLK_DIV 4
56 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
61 #define CONFIG_IDE_RESET 1
62 #define CONFIG_SYS_PIO_MODE 1
63 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
64 #define CONFIG_SYS_IDE_MAXDEVICE 1
65 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
66 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
67 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
68 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
69 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
70 #define CONFIG_IDE_SWAP_IO
73 * SuperH PCI Bridge Configration
75 #define CONFIG_SH4_PCI
76 #define CONFIG_SH7751_PCI
77 #define CONFIG_PCI_SCAN_SHOW 1
80 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
81 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
82 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
83 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
84 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
86 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
87 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
88 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
90 #endif /* __CONFIG_H */