4 #define CONFIG_CPU_SH7751 1
5 #define __LITTLE_ENDIAN__ 1
7 #define CONFIG_DISPLAY_BOARDINFO
10 #define CONFIG_CONS_SCIF1 1
12 #define CONFIG_ENV_OVERWRITE 1
15 #define CONFIG_SYS_SDRAM_BASE 0x8C000000
16 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
18 #define CONFIG_SYS_LONGHELP
19 #define CONFIG_SYS_PBSIZE 256
21 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
22 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
24 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
25 /* Address of u-boot image in Flash */
26 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
27 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
28 /* Size of DRAM reserved for malloc() use */
29 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
30 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
33 * NOR Flash ( Spantion S29GL256P )
35 #define CONFIG_SYS_FLASH_CFI
36 #define CONFIG_FLASH_CFI_DRIVER
37 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
38 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
39 #define CONFIG_SYS_MAX_FLASH_SECT 256
40 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
42 #define CONFIG_ENV_SECT_SIZE 0x40000
43 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
44 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
47 * SuperH Clock setting
49 #define CONFIG_SYS_CLK_FREQ 60000000
50 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
51 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
52 #define CONFIG_SYS_TMU_CLK_DIV 4
53 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
58 #define CONFIG_IDE_RESET 1
59 #define CONFIG_SYS_PIO_MODE 1
60 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
61 #define CONFIG_SYS_IDE_MAXDEVICE 1
62 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
63 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
64 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
65 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
66 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
67 #define CONFIG_IDE_SWAP_IO
70 * SuperH PCI Bridge Configration
72 #define CONFIG_SH4_PCI
73 #define CONFIG_SH7751_PCI
74 #define CONFIG_PCI_SCAN_SHOW 1
77 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
78 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
79 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
80 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
81 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
82 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
83 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
84 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
85 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
87 #endif /* __CONFIG_H */