6 #define CONFIG_CPU_SH7751 1
7 #define CONFIG_CPU_SH_TYPE_R 1
8 #define CONFIG_R2DPLUS 1
9 #define __LITTLE_ENDIAN__ 1
12 * Command line configuration.
14 #include <config_cmd_default.h>
16 #define CONFIG_CMD_CACHE
17 #define CONFIG_CMD_FLASH
18 #define CONFIG_CMD_PCI
19 #define CONFIG_CMD_PING
20 #define CONFIG_CMD_IDE
21 #define CONFIG_CMD_EXT2
22 #define CONFIG_DOS_PARTITION
23 #define CONFIG_CMD_SH_ZIMAGEBOOT
26 #define CONFIG_SCIF_CONSOLE 1
27 #define CONFIG_BAUDRATE 115200
28 #define CONFIG_CONS_SCIF1 1
29 #define CONFIG_BOARD_LATE_INIT
31 #define CONFIG_BOOTDELAY -1
32 #define CONFIG_BOOTARGS "console=ttySC0,115200"
33 #define CONFIG_ENV_OVERWRITE 1
36 #define CONFIG_SYS_SDRAM_BASE (0x8C000000)
37 #define CONFIG_SYS_SDRAM_SIZE (0x04000000)
39 #define CONFIG_SYS_TEXT_BASE 0x0FFC0000
40 #define CONFIG_SYS_LONGHELP
41 #define CONFIG_SYS_CBSIZE 256
42 #define CONFIG_SYS_PBSIZE 256
43 #define CONFIG_SYS_MAXARGS 16
44 #define CONFIG_SYS_BARGSIZE 512
46 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
47 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
49 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
50 /* Address of u-boot image in Flash */
51 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
52 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
53 /* Size of DRAM reserved for malloc() use */
54 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
55 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
58 * NOR Flash ( Spantion S29GL256P )
60 #define CONFIG_SYS_FLASH_CFI
61 #define CONFIG_FLASH_CFI_DRIVER
62 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
63 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
64 #define CONFIG_SYS_MAX_FLASH_SECT 256
65 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
67 #define CONFIG_ENV_IS_IN_FLASH
68 #define CONFIG_ENV_SECT_SIZE 0x40000
69 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
70 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
73 * SuperH Clock setting
75 #define CONFIG_SYS_CLK_FREQ 60000000
76 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
77 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
78 #define CONFIG_SYS_TMU_CLK_DIV 4
79 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
84 #define CONFIG_IDE_RESET 1
85 #define CONFIG_SYS_PIO_MODE 1
86 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
87 #define CONFIG_SYS_IDE_MAXDEVICE 1
88 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
89 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
90 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
91 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
92 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
93 #define CONFIG_IDE_SWAP_IO
96 * SuperH PCI Bridge Configration
99 #define CONFIG_SH4_PCI
100 #define CONFIG_SH7751_PCI
101 #define CONFIG_PCI_PNP
102 #define CONFIG_PCI_SCAN_SHOW 1
106 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
107 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
108 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
109 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
110 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
111 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
112 #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
113 #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
114 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
117 * Network device (RTL8139) support
119 #define CONFIG_RTL8139
121 #endif /* __CONFIG_H */