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x86: Remove CONFIG_SYS_EARLY_PCI_INIT
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1 /*
2  * Configuration for AMCC 460SX Ref (redwood)
3  *
4  * (C) Copyright 2008
5  * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*-----------------------------------------------------------------------
13  * High Level Configuration Options
14  *----------------------------------------------------------------------*/
15 #define CONFIG_440                      1       /* ... PPC460 family    */
16 #define CONFIG_460SX                    1       /* ... PPC460 family    */
17 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init  */
18
19 #define CONFIG_SYS_TEXT_BASE    0xfffb0000
20
21 /*-----------------------------------------------------------------------
22  * Include common defines/options for all AMCC boards
23  *----------------------------------------------------------------------*/
24 #define CONFIG_HOSTNAME         redwood
25
26 #include "amcc-common.h"
27
28 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
29
30 /*-----------------------------------------------------------------------
31  * Base addresses -- Note these are effective addresses where the
32  * actual resources get mapped (not physical addresses)
33  *----------------------------------------------------------------------*/
34 #define CONFIG_SYS_FLASH_BASE           0xfff00000      /* start of FLASH       */
35 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
36
37 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
38
39 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
40 #define CONFIG_SYS_PCIE0_MEMBASE        0x90000000      /* mapped PCIe memory   */
41 #define CONFIG_SYS_PCIE1_MEMBASE        0xa0000000      /* mapped PCIe memory   */
42 #define CONFIG_SYS_PCIE_MEMSIZE 0x01000000
43
44 #define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000
45 #define CONFIG_SYS_PCIE1_XCFGBASE       0xb2000000
46 #define CONFIG_SYS_PCIE2_XCFGBASE       0xb4000000
47 #define CONFIG_SYS_PCIE0_CFGBASE        0xb6000000
48 #define CONFIG_SYS_PCIE1_CFGBASE        0xb8000000
49 #define CONFIG_SYS_PCIE2_CFGBASE        0xba000000
50
51 /* PCIe mapped UTL registers */
52 #define CONFIG_SYS_PCIE0_REGBASE   0xd0000000
53 #define CONFIG_SYS_PCIE1_REGBASE   0xd0010000
54 #define CONFIG_SYS_PCIE2_REGBASE   0xd0020000
55
56 /* System RAM mapped to PCI space */
57 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
58 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
59 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
60
61 #define CONFIG_SYS_FPGA_BASE            0xe2000000      /* epld                 */
62 #define CONFIG_SYS_OPER_FLASH           0xe7000000      /* SRAM - OPER Flash    */
63
64 /*
65  * Serial Port
66  */
67 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
68
69 /*-----------------------------------------------------------------------
70  * Initial RAM & stack pointer (placed in internal SRAM)
71  *----------------------------------------------------------------------*/
72 #define CONFIG_SYS_TEMP_STACK_OCM       1
73 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
74 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
75 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
76
77 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
78 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
79
80 /*-----------------------------------------------------------------------
81  * DDR SDRAM
82  *----------------------------------------------------------------------*/
83 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
84 #define CONFIG_DDR_ECC          1       /* with ECC support             */
85
86 #define CONFIG_SYS_SPD_MAX_DIMMS        2
87
88 /* SPD i2c spd addresses */
89 #define SPD_EEPROM_ADDRESS     {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
90 #define IIC0_DIMM0_ADDR                0x53
91 #define IIC0_DIMM1_ADDR                0x52
92
93 /*-----------------------------------------------------------------------
94  * I2C
95  *----------------------------------------------------------------------*/
96 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
97
98 #define IIC0_BOOTPROM_ADDR      0x50
99 #define IIC0_ALT_BOOTPROM_ADDR  0x54
100
101 /* Don't probe these addrs */
102 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
103
104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
105
106 /*-----------------------------------------------------------------------
107  * Environment
108  *----------------------------------------------------------------------*/
109 #undef  CONFIG_ENV_IS_IN_NVRAM          /* ... not in NVRAM             */
110 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
111 #undef  CONFIG_ENV_IS_IN_EEPROM         /* ... not in EEPROM            */
112
113 #define CONFIG_PREBOOT  "echo;" \
114         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
115         "echo"
116
117 #undef  CONFIG_BOOTARGS
118
119 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
120         CONFIG_AMCC_DEF_ENV                                             \
121         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
122         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
123         "kernel_addr=fc000000\0"                                        \
124         "fdt_addr=fc1e0000\0"                                           \
125         "ramdisk_addr=fc200000\0"                                       \
126         ""
127
128 /*----------------------------------------------------------------------------+
129 | Commands in addition to amcc-common.h
130 +----------------------------------------------------------------------------*/
131 #define CONFIG_CMD_SDRAM
132
133 #define CONFIG_BOOTCOMMAND      "run flash_self"
134
135 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
136
137 #define CONFIG_IBM_EMAC4_V4     1
138 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
139 #define CONFIG_PHY_RESET_DELAY  1000
140 #define CONFIG_M88E1141_PHY     1       /* Enable phy */
141 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
142
143 #define CONFIG_HAS_ETH0
144 #define CONFIG_HAS_ETH1
145 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
146 #define CONFIG_PHY1_ADDR        1       /* PHY address, See schematics  */
147
148 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
149
150 /*-----------------------------------------------------------------------
151  * FLASH related
152  *----------------------------------------------------------------------*/
153 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
154 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
155 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1        /* Use AMD (Spansion) reset cmd */
156
157 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* number of banks              */
158 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* sectors per device           */
159
160 #undef  CONFIG_SYS_FLASH_CHECKSUM
161 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
163
164 #ifdef CONFIG_ENV_IS_IN_FLASH
165 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
166 #define CONFIG_ENV_ADDR         0xfffa0000
167 #define CONFIG_ENV_SIZE         0x10000 /* Size of Environment vars     */
168 #endif /* CONFIG_ENV_IS_IN_FLASH */
169
170 /*---------------------------------------------------------------------------*/
171
172 #endif  /* __CONFIG_H */