3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuration settings for the SACSng 8260 board.
15 * SPDX-License-Identifier: GPL-2.0+
21 #define CONFIG_SYS_TEXT_BASE 0x40000000
23 #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
25 #undef CONFIG_LOGBUFFER /* External logbuffer support */
27 /*****************************************************************************
29 * These settings must match the way _your_ board is set up
31 *****************************************************************************/
33 /* What is the oscillator's (UX2) frequency in Hz? */
34 #define CONFIG_8260_CLKIN 66666600
36 /*-----------------------------------------------------------------------
37 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
38 *-----------------------------------------------------------------------
39 * What should MODCK_H be? It is dependent on the oscillator
40 * frequency, MODCK[1-3], and desired CPM and core frequencies.
41 * Here are some example values (all frequencies are in MHz):
43 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
44 * ------- ---------- --- --- ---- ----- ----- -----
45 * 0x1 0x5 33 100 133 Open Close Open
46 * 0x1 0x6 33 100 166 Open Open Close
47 * 0x1 0x7 33 100 200 Open Open Open
49 * 0x2 0x2 33 133 133 Close Open Close
50 * 0x2 0x3 33 133 166 Close Open Open
51 * 0x2 0x4 33 133 200 Open Close Close
52 * 0x2 0x5 33 133 233 Open Close Open
53 * 0x2 0x6 33 133 266 Open Open Close
55 * 0x5 0x5 66 133 133 Open Close Open
56 * 0x5 0x6 66 133 166 Open Open Close
57 * 0x5 0x7 66 133 200 Open Open Open
58 * 0x6 0x0 66 133 233 Close Close Close
59 * 0x6 0x1 66 133 266 Close Close Open
60 * 0x6 0x2 66 133 300 Close Open Close
62 #define CONFIG_SYS_SBC_MODCK_H 0x05
64 /* Define this if you want to boot from 0x00000100. If you don't define
65 * this, you will need to program the bootloader to 0xfff00000, and
66 * get the hardware reset config words at 0xfe000000. The simplest
67 * way to do that is to program the bootloader at both addresses.
68 * It is suggested that you just let U-Boot live at 0x00000000.
70 #define CONFIG_SYS_SBC_BOOT_LOW 1
72 /* What should the base address of the main FLASH be and how big is
73 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
74 * The main FLASH is whichever is connected to *CS0.
76 #define CONFIG_SYS_FLASH0_BASE 0x40000000
77 #define CONFIG_SYS_FLASH0_SIZE 2
79 /* What should the base address of the secondary FLASH be and how big
80 * is it (in Mbytes)? The secondary FLASH is whichever is connected
83 #define CONFIG_SYS_FLASH1_BASE 0x60000000
84 #define CONFIG_SYS_FLASH1_SIZE 2
86 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
88 #define CONFIG_VERY_BIG_RAM 1
90 /* What should be the base address of SDRAM DIMM and how big is
91 * it (in Mbytes)? This will normally auto-configure via the SPD.
93 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
94 #define CONFIG_SYS_SDRAM0_SIZE 64
97 * Memory map example with 64 MB DIMM:
99 * 0x0000 0000 Exception Vector code, 8k
102 * 0x0000 2000 Free for Application Use
108 * 0x03F5 FF30 Monitor Stack (Growing downward)
109 * Monitor Stack Buffer (0x80)
110 * 0x03F5 FFB0 Board Info Data
111 * 0x03F6 0000 Malloc Arena
112 * : CONFIG_ENV_SECT_SIZE, 16k
113 * : CONFIG_SYS_MALLOC_LEN, 128k
114 * 0x03FC 0000 RAM Copy of Monitor Code
115 * : CONFIG_SYS_MONITOR_LEN, 256k
116 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
119 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
124 * select serial console configuration
126 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
127 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
130 * if CONFIG_CONS_NONE is defined, then the serial console routines must
133 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
134 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
135 #undef CONFIG_CONS_NONE /* define if console on neither */
136 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
139 * select ethernet configuration
141 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
142 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
145 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
146 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
149 #undef CONFIG_ETHER_ON_SCC
150 #define CONFIG_ETHER_ON_FCC
151 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
153 #ifdef CONFIG_ETHER_ON_SCC
154 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
155 #endif /* CONFIG_ETHER_ON_SCC */
157 #ifdef CONFIG_ETHER_ON_FCC
158 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
159 #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
160 #define CONFIG_MII /* MII PHY management */
161 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
163 * Port pins used for bit-banged MII communictions (if applicable).
166 #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
167 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
168 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
169 #define MDC_DECLARE MDIO_DECLARE
171 #define MDIO_ACTIVE (iop->pdir |= 0x40000000)
172 #define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
173 #define MDIO_READ ((iop->pdat & 0x40000000) != 0)
175 #define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
176 else iop->pdat &= ~0x40000000
178 #define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
179 else iop->pdat &= ~0x80000000
181 #define MIIDELAY udelay(50)
182 #endif /* CONFIG_ETHER_ON_FCC */
184 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
190 # define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
192 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
197 * - Select bus for bd/buffers (see 28-13)
198 * - Enable Full Duplex in FSMR
200 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
201 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
202 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
203 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
205 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
207 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
210 * Configure for RAM tests.
212 #undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */
216 * Status LED for power up status feedback.
218 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
220 #define STATUS_LED_PAR im_ioport.iop_ppara
221 #define STATUS_LED_DIR im_ioport.iop_pdira
222 #define STATUS_LED_ODR im_ioport.iop_podra
223 #define STATUS_LED_DAT im_ioport.iop_pdata
225 #define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
226 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ)
227 #define STATUS_LED_STATE STATUS_LED_OFF
228 #define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
229 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
230 #define STATUS_LED_STATE1 STATUS_LED_OFF
231 #define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
232 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2)
233 #define STATUS_LED_STATE2 STATUS_LED_ON
235 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
237 #define STATUS_LED_YELLOW 0
238 #define STATUS_LED_GREEN 1
239 #define STATUS_LED_RED 2
240 #define STATUS_LED_BOOT 1
244 * Select SPI support configuration
246 #define CONFIG_SOFT_SPI /* Enable SPI driver */
247 #define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
248 #undef DEBUG_SPI /* Disable SPI debugging */
251 * Software (bit-bang) SPI driver configuration
253 #ifdef CONFIG_SOFT_SPI
256 * Software (bit-bang) SPI driver configuration
258 #define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
259 #define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
260 #define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
262 #undef SPI_INIT /* no port initialization needed */
263 #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
264 #define SPI_SDA(bit) do { \
265 if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
266 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
268 #define SPI_SCL(bit) do { \
269 if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
270 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
272 #define SPI_DELAY /* No delay is needed */
273 #endif /* CONFIG_SOFT_SPI */
277 * select I2C support configuration
279 * Supported configurations are {none, software, hardware} drivers.
280 * If the software driver is chosen, there are some additional
281 * configuration items that the driver uses to drive the port pins.
283 #undef CONFIG_HARD_I2C /* I2C with hardware support */
284 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
285 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
286 #define CONFIG_SYS_I2C_SLAVE 0x7F
289 * Software (bit-bang) I2C driver configuration
291 #ifdef CONFIG_SOFT_I2C
292 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
293 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
294 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
295 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
296 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
297 else iop->pdat &= ~0x00010000
298 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
299 else iop->pdat &= ~0x00020000
300 #define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
301 #endif /* CONFIG_SOFT_I2C */
303 /* Define this to reserve an entire FLASH sector for
304 * environment variables. Otherwise, the environment will be
305 * put in the same sector as U-Boot, and changing variables
306 * will erase U-Boot temporarily
308 #define CONFIG_ENV_IN_OWN_SECT 1
310 /* Define this to contain any number of null terminated strings that
311 * will be part of the default enviroment compiled into the boot image.
313 #define CONFIG_EXTRA_ENV_SETTINGS \
315 "serverip=192.168.123.205\0" \
316 "ipaddr=192.168.123.203\0" \
317 "checkhostname=VR8500\0" \
320 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
321 "protect off 60000000 6003FFFF; " \
322 "erase 60000000 6003FFFF; " \
323 "cp.b 140000 60000000 ${filesize}; " \
324 "protect on 60000000 6003FFFF\0" \
326 "protect off 60040000 6004FFFF; " \
327 "erase 60040000 6004FFFF; " \
328 "cp.b 40040000 60040000 10000; " \
329 "protect on 60040000 6004FFFF\0" \
331 "protect off 60000000 6003FFFF; " \
332 "erase 60000000 6003FFFF; " \
333 "cp.b 40000000 60000000 40000; " \
334 "protect on 60000000 6003FFFF\0" \
336 "protect off 40040000 4004FFFF; " \
337 "erase 40040000 4004FFFF; " \
338 "protect on 40040000 4004FFFF\0" \
340 "protect off 60040000 6004FFFF; " \
341 "erase 60040000 6004FFFF; " \
342 "protect on 60040000 6004FFFF\0" \
348 "setenv bootargs root=/dev/ram0 rw quiet " \
349 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
352 "root-on-initrd-debug="\
357 "setenv bootargs root=/dev/ram0 rw debug " \
358 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
359 "run debug-hook\\;" \
367 "setenv bootargs root=/dev/nfs rw quiet " \
368 "nfsroot=\\${serverip}:\\${rootpath} " \
369 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
372 "root-on-nfs-debug="\
377 "setenv bootargs root=/dev/nfs rw debug " \
378 "nfsroot=\\${serverip}:\\${rootpath} " \
379 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
380 "run debug-hook\\;" \
384 "setenv checkhostname;" \
385 "setenv ethaddr 00:09:70:00:00:01;" \
387 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
388 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
393 "echo ipaddr ${ipaddr};" \
394 "echo serverip ${serverip};" \
395 "echo gatewayip ${gatewayip};" \
396 "echo netmask ${netmask};" \
397 "echo hostname ${hostname}\0" \
398 "ana=run adc ; run dac\0" \
399 "adc=run adc-12 ; run adc-34\0" \
400 "adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
401 "adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
402 "dac=echo ### DAC ; i2c md 11 81 5\0" \
405 /* What should the console's baud rate be? */
406 #define CONFIG_BAUDRATE 9600
408 /* Ethernet MAC address */
409 #define CONFIG_ETHADDR 00:09:70:00:00:00
411 /* The default Ethernet MAC address can be overwritten just once */
412 #ifdef CONFIG_ETHADDR
413 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
417 * Define this to do some miscellaneous board-specific initialization.
419 #define CONFIG_MISC_INIT_R
421 /* Set to a positive value to delay for running BOOTCOMMAND */
422 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
424 /* Be selective on what keys can delay or stop the autoboot process
427 #define CONFIG_AUTOBOOT_KEYED
428 #define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
429 #define CONFIG_AUTOBOOT_STOP_STR " "
430 #undef CONFIG_AUTOBOOT_DELAY_STR
431 #define CONFIG_ZERO_BOOTDELAY_CHECK
432 #define DEBUG_BOOTKEYS 0
434 /* Define a command string that is automatically executed when no character
435 * is read on the console interface withing "Boot Delay" after reset.
437 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
438 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
440 #ifdef CONFIG_BOOT_ROOT_INITRD
441 #define CONFIG_BOOTCOMMAND \
445 "setenv bootargs root=/dev/ram0 rw quiet " \
446 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
449 #endif /* CONFIG_BOOT_ROOT_INITRD */
451 #ifdef CONFIG_BOOT_ROOT_NFS
452 #define CONFIG_BOOTCOMMAND \
456 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
457 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
460 #endif /* CONFIG_BOOT_ROOT_NFS */
462 #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
467 #define CONFIG_BOOTP_SUBNETMASK
468 #define CONFIG_BOOTP_GATEWAY
469 #define CONFIG_BOOTP_HOSTNAME
470 #define CONFIG_BOOTP_BOOTPATH
471 #define CONFIG_BOOTP_BOOTFILESIZE
472 #define CONFIG_BOOTP_DNS
473 #define CONFIG_BOOTP_DNS2
474 #define CONFIG_BOOTP_SEND_HOSTNAME
477 /* undef this to save memory */
478 #define CONFIG_SYS_LONGHELP
480 /* Monitor Command Prompt */
481 #define CONFIG_SYS_PROMPT "=> "
483 #undef CONFIG_SYS_HUSH_PARSER
484 #ifdef CONFIG_SYS_HUSH_PARSER
487 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
488 * of an image is printed by image commands like bootm or iminfo.
490 #define CONFIG_TIMESTAMP
492 /* If this variable is defined, an environment variable named "ver"
493 * is created by U-Boot showing the U-Boot version.
495 #define CONFIG_VERSION_VARIABLE
499 * Command line configuration.
501 #include <config_cmd_default.h>
503 #define CONFIG_CMD_ELF
504 #define CONFIG_CMD_ASKENV
505 #define CONFIG_CMD_I2C
506 #define CONFIG_CMD_SPI
507 #define CONFIG_CMD_SDRAM
508 #define CONFIG_CMD_REGINFO
509 #define CONFIG_CMD_IMMAP
510 #define CONFIG_CMD_IRQ
511 #define CONFIG_CMD_PING
513 #undef CONFIG_CMD_KGDB
515 #ifdef CONFIG_ETHER_ON_FCC
516 #define CONFIG_CMD_MII
520 /* Where do the internal registers live? */
521 #define CONFIG_SYS_IMMR 0xF0000000
523 #undef CONFIG_WATCHDOG /* disable the watchdog */
525 /*****************************************************************************
527 * You should not have to modify any of the following settings
529 *****************************************************************************/
531 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
532 #define CONFIG_SACSng 1 /* munged for the SACSng */
533 #define CONFIG_CPM2 1 /* Has a CPM2 */
536 * Miscellaneous configurable options
538 #define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
539 /* in the bootm command. */
540 #define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
541 /* "## <message>" from the bootm cmd */
542 #define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
543 /* defined, then the hostname param */
544 /* validated against checkhostname. */
545 #define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
546 #define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
547 /* (limited to maximum of 1024 msec) */
548 #define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
549 /* Check for abort key presses */
550 /* at least once in dependent of the */
551 /* CONFIG_BOOTDELAY value. */
552 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
553 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
554 /* state to the fault LED. */
555 #define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
556 /* the Ethernet link state. */
557 #define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
558 /* until the TFTP is successful. */
559 #define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
560 /* turn off the STATUS LEDs. */
561 #define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
563 #define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
564 /* to signify that tftp is moving. */
565 #define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
566 /* flash the status LED. */
567 #define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
568 /* during the tftp file transfer. */
569 #define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
570 /* '#'s from the tftp command. */
571 #define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
572 /* issued during the tftp command. */
573 #define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
574 /* before it gives up. */
576 #if defined(CONFIG_CMD_KGDB)
577 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
579 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
582 /* Print Buffer Size */
583 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
585 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
587 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
589 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
590 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
592 #define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
593 #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
594 /* the exception vector table */
595 /* to the end of the DRAM */
596 /* less monitor and malloc area */
597 #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
598 #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
599 + CONFIG_SYS_MALLOC_LEN \
600 + CONFIG_ENV_SECT_SIZE \
601 + CONFIG_SYS_STACK_USAGE )
603 #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
604 - CONFIG_SYS_MEM_END_USAGE )
607 * Low Level Configuration Settings
608 * (address mappings, register initial values, etc.)
609 * You should know what you are doing if you make changes here.
612 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
613 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
614 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
615 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
617 /*-----------------------------------------------------------------------
618 * Hard Reset Configuration Words
620 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
621 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
623 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
624 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
626 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
627 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
628 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
629 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
631 #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \
633 CONFIG_SYS_SBC_HRCW_IMMR | \
638 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
639 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
642 #define CONFIG_SYS_HRCW_SLAVE1 0
643 #define CONFIG_SYS_HRCW_SLAVE2 0
644 #define CONFIG_SYS_HRCW_SLAVE3 0
645 #define CONFIG_SYS_HRCW_SLAVE4 0
646 #define CONFIG_SYS_HRCW_SLAVE5 0
647 #define CONFIG_SYS_HRCW_SLAVE6 0
648 #define CONFIG_SYS_HRCW_SLAVE7 0
650 /*-----------------------------------------------------------------------
651 * Definitions for initial stack pointer and data area (in DPRAM)
653 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
654 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
655 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
656 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
658 /*-----------------------------------------------------------------------
659 * Start addresses for the final memory configuration
660 * (Set up by the startup code)
661 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
662 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
664 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
666 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
667 # define CONFIG_SYS_RAMBOOT
670 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
671 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
674 * For booting Linux, the board info and command line data
675 * have to be in the first 8 MB of memory, since this is
676 * the maximum mapped by the Linux kernel during initialization.
678 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
680 /*-----------------------------------------------------------------------
681 * FLASH and environment organization
684 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
685 #undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
686 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
687 #define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
689 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
690 #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
692 #ifndef CONFIG_SYS_RAMBOOT
693 # define CONFIG_ENV_IS_IN_FLASH 1
695 # ifdef CONFIG_ENV_IN_OWN_SECT
696 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
697 # define CONFIG_ENV_SECT_SIZE 0x10000
699 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
700 # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
701 # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
702 # endif /* CONFIG_ENV_IN_OWN_SECT */
705 # define CONFIG_ENV_IS_IN_NVRAM 1
706 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
707 # define CONFIG_ENV_SIZE 0x200
708 #endif /* CONFIG_SYS_RAMBOOT */
710 /*-----------------------------------------------------------------------
711 * Cache Configuration
713 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
715 #if defined(CONFIG_CMD_KGDB)
716 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
719 /*-----------------------------------------------------------------------
720 * HIDx - Hardware Implementation-dependent Registers 2-11
721 *-----------------------------------------------------------------------
722 * HID0 also contains cache control - initially enable both caches and
723 * invalidate contents, then the final state leaves only the instruction
724 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
725 * but Soft reset does not.
727 * HID1 has only read-only information - nothing to set.
729 #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
736 #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
740 #define CONFIG_SYS_HID2 0
742 /*-----------------------------------------------------------------------
743 * RMR - Reset Mode Register
744 *-----------------------------------------------------------------------
746 #define CONFIG_SYS_RMR 0
748 /*-----------------------------------------------------------------------
749 * BCR - Bus Configuration 4-25
750 *-----------------------------------------------------------------------
752 #define CONFIG_SYS_BCR (BCR_ETM)
754 /*-----------------------------------------------------------------------
755 * SIUMCR - SIU Module Configuration 4-31
756 *-----------------------------------------------------------------------
759 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
765 /*-----------------------------------------------------------------------
766 * SYPCR - System Protection Control 11-9
767 * SYPCR can only be written once after reset!
768 *-----------------------------------------------------------------------
769 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
771 #if defined(CONFIG_WATCHDOG)
772 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
780 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
786 #endif /* CONFIG_WATCHDOG */
788 /*-----------------------------------------------------------------------
789 * TMCNTSC - Time Counter Status and Control 4-40
790 *-----------------------------------------------------------------------
791 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
792 * and enable Time Counter
794 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
799 /*-----------------------------------------------------------------------
800 * PISCR - Periodic Interrupt Status and Control 4-42
801 *-----------------------------------------------------------------------
802 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
805 #define CONFIG_SYS_PISCR (PISCR_PS |\
809 /*-----------------------------------------------------------------------
810 * SCCR - System Clock Control 9-8
811 *-----------------------------------------------------------------------
813 #define CONFIG_SYS_SCCR 0
815 /*-----------------------------------------------------------------------
816 * RCCR - RISC Controller Configuration 13-7
817 *-----------------------------------------------------------------------
819 #define CONFIG_SYS_RCCR 0
822 * Initialize Memory Controller:
824 * Bank Bus Machine PortSz Device
825 * ---- --- ------- ------ ------
826 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
827 * 1 60x GPCM -- bit (Unused)
828 * 2 60x SDRAM 64 bit SDRAM (DIMM)
829 * 3 60x SDRAM 64 bit SDRAM (DIMM)
830 * 4 60x GPCM -- bit (Unused)
831 * 5 60x GPCM -- bit (Unused)
832 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
835 /*-----------------------------------------------------------------------
836 * BR0,BR1 - Base Register
837 * Ref: Section 10.3.1 on page 10-14
838 * OR0,OR1 - Option Register
839 * Ref: Section 10.3.2 on page 10-18
840 *-----------------------------------------------------------------------
843 /* Bank 0 - Primary FLASH
846 /* BR0 is configured as follows:
848 * - Base address of 0x40000000
850 * - Data errors checking is disabled
851 * - Read and write access
853 * - Access are handled by the memory controller according to MSEL
854 * - Not used for atomic operations
855 * - No data pipelining is done
858 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
863 /* OR0 is configured as follows:
866 * - *BCTL0 is asserted upon access to the current memory bank
867 * - *CW / *WE are negated a quarter of a clock earlier
868 * - *CS is output at the same time as the address lines
869 * - Uses a clock cycle length of 5
870 * - *PSDVAL is generated internally by the memory controller
871 * unless *GTA is asserted earlier externally.
872 * - Relaxed timing is generated by the GPCM for accesses
873 * initiated to this memory region.
874 * - One idle clock is inserted between a read access from the
875 * current bank and the next access.
877 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
884 /*-----------------------------------------------------------------------
885 * BR2,BR3 - Base Register
886 * Ref: Section 10.3.1 on page 10-14
887 * OR2,OR3 - Option Register
888 * Ref: Section 10.3.2 on page 10-16
889 *-----------------------------------------------------------------------
892 /* Bank 2,3 - SDRAM DIMM
895 /* The BR2 is configured as follows:
897 * - Base address of 0x00000000
898 * - 64 bit port size (60x bus only)
899 * - Data errors checking is disabled
900 * - Read and write access
902 * - Access are handled by the memory controller according to MSEL
903 * - Not used for atomic operations
904 * - No data pipelining is done
907 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
912 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
917 /* With a 64 MB DIMM, the OR2 is configured as follows:
920 * - 4 internal banks per device
921 * - Row start address bit is A8 with PSDMR[PBI] = 0
922 * - 12 row address lines
923 * - Back-to-back page mode
924 * - Internal bank interleaving within save device enabled
926 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
927 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
929 ORxS_ROWST_PBI0_A8 |\
932 #error "INVALID SDRAM CONFIGURATION"
935 /*-----------------------------------------------------------------------
936 * PSDMR - 60x Bus SDRAM Mode Register
937 * Ref: Section 10.3.3 on page 10-21
938 *-----------------------------------------------------------------------
941 /* Address that the DIMM SPD memory lives at.
943 #define SDRAM_SPD_ADDR 0x50
945 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
946 /* With a 64 MB DIMM, the PSDMR is configured as follows:
948 * - Bank Based Interleaving,
950 * - Address Multiplexing where A5 is output on A14 pin
951 * (A6 on A15, and so on),
952 * - use address pins A14-A16 as bank select,
953 * - A9 is output on SDA10 during an ACTIVATE command,
954 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
955 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
957 * - earliest timing for READ/WRITE command after ACTIVATE command is
959 * - earliest timing for PRECHARGE after last data was read is 1 clock,
960 * - earliest timing for PRECHARGE after last data was written is 1 clock,
961 * - CAS Latency is 2.
963 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
964 PSDMR_SDAM_A14_IS_A5 |\
965 PSDMR_BSMA_A14_A16 |\
966 PSDMR_SDA10_PBI0_A9 |\
974 #error "INVALID SDRAM CONFIGURATION"
978 * Shoot for approximately 1MHz on the prescaler.
980 #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
981 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
982 #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
983 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
985 #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
986 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
988 #define CONFIG_SYS_PSRT 14
991 /*-----------------------------------------------------------------------
992 * BR6 - Base Register
993 * Ref: Section 10.3.1 on page 10-14
994 * OR6 - Option Register
995 * Ref: Section 10.3.2 on page 10-18
996 *-----------------------------------------------------------------------
999 /* Bank 6 - Secondary FLASH
1001 * The secondary FLASH is connected to *CS6
1003 #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
1005 /* BR6 is configured as follows:
1007 * - Base address of 0x60000000
1008 * - 16 bit port size
1009 * - Data errors checking is disabled
1010 * - Read and write access
1012 * - Access are handled by the memory controller according to MSEL
1013 * - Not used for atomic operations
1014 * - No data pipelining is done
1017 # define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
1022 /* OR6 is configured as follows:
1025 * - *BCTL0 is asserted upon access to the current memory bank
1026 * - *CW / *WE are negated a quarter of a clock earlier
1027 * - *CS is output at the same time as the address lines
1028 * - Uses a clock cycle length of 5
1029 * - *PSDVAL is generated internally by the memory controller
1030 * unless *GTA is asserted earlier externally.
1031 * - Relaxed timing is generated by the GPCM for accesses
1032 * initiated to this memory region.
1033 * - One idle clock is inserted between a read access from the
1034 * current bank and the next access.
1036 # define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
1042 #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
1044 #endif /* __CONFIG_H */