git.sur5r.net Git - u-boot/blob - include/configs/sama5d3xek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the SAMA5D3xEK board.
   4  *
   5  * Copyright (C) 2012 - 2013 Atmel
   6  *
   7  * based on at91sam9m10g45ek.h by:
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #include "at91-sama5_common.h"
  16
  17 /*
  18  * This needs to be defined for the OHCI code to work but it is defined as
  19  * ATMEL_ID_UHPHS in the CPU specific header files.
  20  */
  21 #define ATMEL_ID_UHP                    32
  22
  23 /*
  24  * Specify the clock enable bit in the PMC_SCER register.
  25  */
  26 #define ATMEL_PMC_UHP                   (1 <<  6)
  27
  28 /* board specific (not enough SRAM) */
  29 #define CONFIG_SAMA5D3_LCD_BASE         0x23E00000
  30
  31 /* NOR flash */
  32 #ifdef CONFIG_MTD_NOR_FLASH
  33 #define CONFIG_FLASH_CFI_DRIVER
  34 #define CONFIG_SYS_FLASH_CFI
  35 #define CONFIG_SYS_FLASH_PROTECTION
  36 #define CONFIG_SYS_FLASH_BASE           0x10000000
  37 #define CONFIG_SYS_MAX_FLASH_SECT       131
  38 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  39 #endif
  40
  41 /* SDRAM */
  42 #define CONFIG_NR_DRAM_BANKS            1
  43 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  44 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  45
  46 #ifdef CONFIG_SPL_BUILD
  47 #define CONFIG_SYS_INIT_SP_ADDR         0x318000
  48 #else
  49 #define CONFIG_SYS_INIT_SP_ADDR \
  50         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  51 #endif
  52
  53 /* SerialFlash */
  54
  55 #ifdef CONFIG_CMD_SF
  56 #define CONFIG_SF_DEFAULT_SPEED         30000000
  57 #endif
  58
  59 /* NAND flash */
  60 #ifdef CONFIG_CMD_NAND
  61 #define CONFIG_NAND_ATMEL
  62 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  63 #define CONFIG_SYS_NAND_BASE            0x60000000
  64 /* our ALE is AD21 */
  65 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  66 /* our CLE is AD22 */
  67 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  68 #define CONFIG_SYS_NAND_ONFI_DETECTION
  69 #endif
  70 /* PMECC & PMERRLOC */
  71 #define CONFIG_ATMEL_NAND_HWECC
  72 #define CONFIG_ATMEL_NAND_HW_PMECC
  73 #define CONFIG_PMECC_CAP                4
  74 #define CONFIG_PMECC_SECTOR_SIZE        512
  75
  76 /* USB */
  77
  78 #ifdef CONFIG_CMD_USB
  79 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  80 #define CONFIG_USB_OHCI_NEW
  81 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  82 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_BASE_OHCI
  83 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "sama5d3"
  84 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
  85 #endif
  86
  87 #define CONFIG_SYS_LOAD_ADDR                    0x22000000 /* load address */
  88
  89 /* SPL */
  90 #define CONFIG_SPL_TEXT_BASE            0x300000
  91 #define CONFIG_SPL_MAX_SIZE             0x18000
  92 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  93 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  94 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  95 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  96
  97 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  98
  99 #ifdef CONFIG_SD_BOOT
 100 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 101 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 102
 103 #elif CONFIG_SPI_BOOT
 104 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x10000
 105
 106 #elif CONFIG_NAND_BOOT
 107 #define CONFIG_SPL_NAND_DRIVERS
 108 #define CONFIG_SPL_NAND_BASE
 109 #endif
 110 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 111 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 112 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 113 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 114 #define CONFIG_SYS_NAND_OOBSIZE         64
 115 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 116 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
 117 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 118
 119 #endif