2 * Copyright (c) 2011 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
12 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
13 #define CONFIG_TRACE_EARLY
14 #define CONFIG_TRACE_EARLY_ADDR 0x00100000
18 #ifndef CONFIG_SPL_BUILD
19 #define CONFIG_IO_TRACE
23 #define CONFIG_SYS_TIMER_RATE 1000000
28 #define CONFIG_FS_EXT4
29 #define CONFIG_EXT4_WRITE
30 #define CONFIG_HOST_MAX_DEVICES 4
33 * Size of malloc() pool, before and after relocation
35 #define CONFIG_MALLOC_F_ADDR 0x0010000
36 #define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
38 #define CONFIG_SYS_LONGHELP /* #undef to save memory */
39 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
40 #define CONFIG_DISPLAY_BOARDINFO_LATE
42 /* turn on command-line edit/c/auto */
43 #define CONFIG_CMDLINE_EDITING
44 #define CONFIG_AUTO_COMPLETE
46 #define CONFIG_ENV_SIZE 8192
48 /* SPI - enable all SPI flash types for testing purposes */
50 #define CONFIG_I2C_EDID
52 /* Memory things - we don't really want a memory test */
53 #define CONFIG_SYS_LOAD_ADDR 0x00000000
54 #define CONFIG_SYS_MEMTEST_START 0x00100000
55 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
56 #define CONFIG_SYS_FDT_LOAD_ADDR 0x100
58 #define CONFIG_PHYSMEM
60 /* Size of our emulated memory */
61 #define CONFIG_SYS_SDRAM_BASE 0
62 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
63 #define CONFIG_SYS_TEXT_BASE 0
64 #define CONFIG_SYS_MONITOR_BASE 0
65 #define CONFIG_NR_DRAM_BANKS 1
67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
70 /* include default commands */
71 #include <config_distro_defaults.h>
73 #define BOOT_TARGET_DEVICES(func) \
77 #define CONFIG_BOOTCOMMAND ""
79 #include <config_distro_bootcmd.h>
81 #define CONFIG_KEEP_SERVERADDR
82 #define CONFIG_UDP_CHECKSUM
83 #define CONFIG_TIMESTAMP
84 #define CONFIG_BOOTP_DNS
85 #define CONFIG_BOOTP_DNS2
86 #define CONFIG_BOOTP_SEND_HOSTNAME
87 #define CONFIG_BOOTP_SERVERIP
88 #define CONFIG_IP_DEFRAG
90 #ifndef SANDBOX_NO_SDL
91 #define CONFIG_SANDBOX_SDL
94 /* LCD and keyboard require SDL support */
95 #ifdef CONFIG_SANDBOX_SDL
96 #define LCD_BPP LCD_COLOR16
97 #define CONFIG_LCD_BMP_RLE8
98 #define CONFIG_VIDEO_BMP_RLE8
99 #define CONFIG_SPLASH_SCREEN_ALIGN
101 #define CONFIG_KEYBOARD
103 #define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
104 "stdout=serial,vidconsole\0" \
105 "stderr=serial,vidconsole\0"
107 #define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
108 "stdout=serial,vidconsole\0" \
109 "stderr=serial,vidconsole\0"
112 #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
113 "eth1addr=00:00:11:22:33:45\0" \
114 "eth3addr=00:00:11:22:33:46\0" \
115 "eth5addr=00:00:11:22:33:47\0" \
118 #define MEM_LAYOUT_ENV_SETTINGS \
119 "bootm_size=0x10000000\0" \
120 "kernel_addr_r=0x1000000\0" \
121 "fdt_addr_r=0xc00000\0" \
122 "ramdisk_addr_r=0x2000000\0" \
123 "scriptaddr=0x1000\0" \
124 "pxefile_addr_r=0x2000\0"
126 #define CONFIG_EXTRA_ENV_SETTINGS \
127 SANDBOX_SERIAL_SETTINGS \
128 SANDBOX_ETH_SETTINGS \
130 MEM_LAYOUT_ENV_SETTINGS
132 #define CONFIG_GZIP_COMPRESSED
135 #ifndef CONFIG_SPL_BUILD
136 #define CONFIG_SYS_IDE_MAXBUS 1
137 #define CONFIG_SYS_ATA_IDE0_OFFSET 0
138 #define CONFIG_SYS_IDE_MAXDEVICE 2
139 #define CONFIG_SYS_ATA_BASE_ADDR 0x100
140 #define CONFIG_SYS_ATA_DATA_OFFSET 0
141 #define CONFIG_SYS_ATA_REG_OFFSET 1
142 #define CONFIG_SYS_ATA_ALT_OFFSET 2
143 #define CONFIG_SYS_ATA_STRIDE 4
146 #define CONFIG_SCSI_AHCI_PLAT
147 #define CONFIG_SYS_SCSI_MAX_DEVICE 2
148 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
149 #define CONFIG_SYS_SCSI_MAX_LUN 4
151 #define CONFIG_SYS_SATA_MAX_DEVICE 2
153 #define CONFIG_SYSTEMACE
154 #define CONFIG_SYS_SYSTEMACE_WIDTH 16
155 #define CONFIG_SYS_SYSTEMACE_BASE 0
157 #define CONFIG_MISC_INIT_F