3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 /* Enable debug prints */
39 #undef DEBUG /* General debug */
40 #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
42 /*****************************************************************************
44 * These settings must match the way _your_ board is set up
46 *****************************************************************************/
48 /* What is the oscillator's (UX2) frequency in Hz? */
49 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
51 /*-----------------------------------------------------------------------
52 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
53 *-----------------------------------------------------------------------
54 * What should MODCK_H be? It is dependent on the oscillator
55 * frequency, MODCK[1-3], and desired CPM and core frequencies.
56 * Here are some example values (all frequencies are in MHz):
58 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
59 * ------- ---------- --- --- ---- ----- ----- -----
60 * 0x1 0x5 33 100 133 Open Close Open
61 * 0x1 0x6 33 100 166 Open Open Close
62 * 0x1 0x7 33 100 200 Open Open Open
64 * 0x2 0x2 33 133 133 Close Open Close
65 * 0x2 0x3 33 133 166 Close Open Open
66 * 0x2 0x4 33 133 200 Open Close Close
67 * 0x2 0x5 33 133 233 Open Close Open
68 * 0x2 0x6 33 133 266 Open Open Close
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
77 #define CFG_SBC_MODCK_H 0x05
79 /* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
85 #define CFG_SBC_BOOT_LOW 1
87 /* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
89 * The main FLASH is whichever is connected to *CS0. U-Boot expects
90 * this to be the SIMM.
92 #define CFG_FLASH0_BASE 0x40000000
93 #define CFG_FLASH0_SIZE 4
95 /* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
97 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
98 * want it enabled, don't define these constants.
100 #define CFG_FLASH1_BASE 0x60000000
101 #define CFG_FLASH1_SIZE 2
103 /* What should be the base address of SDRAM DIMM and how big is
106 #define CFG_SDRAM0_BASE 0x00000000
107 #define CFG_SDRAM0_SIZE 64
109 /* What should be the base address of the LEDs and switch S0?
110 * If you don't want them enabled, don't define this.
112 #define CFG_LED_BASE 0xa0000000
116 * SBC8260 with 16 MB DIMM:
118 * 0x0000 0000 Exception Vector code, 8k
121 * 0x0000 2000 Free for Application Use
127 * 0x00F5 FF30 Monitor Stack (Growing downward)
128 * Monitor Stack Buffer (0x80)
129 * 0x00F5 FFB0 Board Info Data
130 * 0x00F6 0000 Malloc Arena
131 * : CFG_ENV_SECT_SIZE, 256k
132 * : CFG_MALLOC_LEN, 128k
133 * 0x00FC 0000 RAM Copy of Monitor Code
134 * : CFG_MONITOR_LEN, 256k
135 * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
139 * SBC8260 with 64 MB DIMM:
141 * 0x0000 0000 Exception Vector code, 8k
144 * 0x0000 2000 Free for Application Use
150 * 0x03F5 FF30 Monitor Stack (Growing downward)
151 * Monitor Stack Buffer (0x80)
152 * 0x03F5 FFB0 Board Info Data
153 * 0x03F6 0000 Malloc Arena
154 * : CFG_ENV_SECT_SIZE, 256k
155 * : CFG_MALLOC_LEN, 128k
156 * 0x03FC 0000 RAM Copy of Monitor Code
157 * : CFG_MONITOR_LEN, 256k
158 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
163 * select serial console configuration
165 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
166 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
169 * if CONFIG_CONS_NONE is defined, then the serial console routines must
172 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
173 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
174 #undef CONFIG_CONS_NONE /* define if console on neither */
175 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
178 * select ethernet configuration
180 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
181 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
184 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
185 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
186 * from CONFIG_COMMANDS to remove support for networking.
189 #undef CONFIG_ETHER_ON_SCC
190 #define CONFIG_ETHER_ON_FCC
191 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
193 #ifdef CONFIG_ETHER_ON_SCC
194 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
195 #endif /* CONFIG_ETHER_ON_SCC */
197 #ifdef CONFIG_ETHER_ON_FCC
198 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
199 #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
200 #define CONFIG_MII /* MII PHY management */
201 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
203 * Port pins used for bit-banged MII communictions (if applicable).
205 #define MDIO_PORT 2 /* Port C */
206 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
207 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
208 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
210 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
211 else iop->pdat &= ~0x00400000
213 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
214 else iop->pdat &= ~0x00200000
216 #define MIIDELAY udelay(1)
217 #endif /* CONFIG_ETHER_ON_FCC */
219 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
225 # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
227 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
232 * - Select bus for bd/buffers (see 28-13)
233 * - Enable Full Duplex in FSMR
235 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
236 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
237 # define CFG_CPMFCR_RAMTYPE 0
238 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
240 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
243 * Select SPI support configuration
245 #undef CONFIG_SPI /* Disable SPI driver */
248 * Select i2c support configuration
250 * Supported configurations are {none, software, hardware} drivers.
251 * If the software driver is chosen, there are some additional
252 * configuration items that the driver uses to drive the port pins.
254 #undef CONFIG_HARD_I2C /* I2C with hardware support */
255 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
256 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
257 #define CFG_I2C_SLAVE 0x7F
260 * Software (bit-bang) I2C driver configuration
262 #ifdef CONFIG_SOFT_I2C
263 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
264 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
265 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
266 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
267 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
268 else iop->pdat &= ~0x00010000
269 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
270 else iop->pdat &= ~0x00020000
271 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
272 #endif /* CONFIG_SOFT_I2C */
275 /* Define this to reserve an entire FLASH sector (256 KB) for
276 * environment variables. Otherwise, the environment will be
277 * put in the same sector as U-Boot, and changing variables
278 * will erase U-Boot temporarily
280 #define CFG_ENV_IN_OWN_SECT 1
282 /* Define to allow the user to overwrite serial and ethaddr */
283 #define CONFIG_ENV_OVERWRITE
285 /* What should the console's baud rate be? */
286 #define CONFIG_BAUDRATE 9600
288 /* Ethernet MAC address
289 * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
290 * http://standards.ieee.org/regauth/oui/index.shtml
292 #define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
295 * Define this to set the last octet of the ethernet address from the
296 * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
297 * switch and the LEDs are backwards with respect to each other. DS7
298 * is on the board edge side of both the LED strip and the DS0-DS7
301 #undef CONFIG_MISC_INIT_R
303 /* Set to a positive value to delay for running BOOTCOMMAND */
304 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
306 /* Be selective on what keys can delay or stop the autoboot process
309 #undef CONFIG_AUTOBOOT_KEYED
310 #ifdef CONFIG_AUTOBOOT_KEYED
311 # define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
312 # define CONFIG_AUTOBOOT_STOP_STR " "
313 # undef CONFIG_AUTOBOOT_DELAY_STR
314 # define DEBUG_BOOTKEYS 0
317 /* Define this to contain any number of null terminated strings that
318 * will be part of the default enviroment compiled into the boot image.
321 * -------------- -------------------------------------------------------
322 * serverip server IP address
323 * ipaddr my IP address
324 * reprog Reload flash with a new copy of U-Boot
325 * zapenv Erase the environment area in flash
326 * root-on-initrd Set the bootcmd variable to allow booting of an initial
328 * root-on-nfs Set the bootcmd variable to allow booting of a NFS
329 * mounted root filesystem.
330 * boot-hook Convenient stub to do something useful before the
331 * bootm command is executed.
333 * Example usage of root-on-initrd and root-on-nfs :
335 * Note: The lines have been wrapped to improved its readability.
337 * => printenv bootcmd
338 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
339 * nfsroot=${serverip}:${rootpath}
340 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
342 * => run root-on-initrd
343 * => printenv bootcmd
344 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
345 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
348 * => printenv bootcmd
349 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
350 * nfsroot=${serverip}:${rootpath}
351 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
354 #define CONFIG_EXTRA_ENV_SETTINGS \
355 "serverip=192.168.123.205\0" \
356 "ipaddr=192.168.123.213\0" \
359 "tftpboot 0x140000 /bdi2000/u-boot.bin;" \
362 "cp.b 140000 40000000 ${filesize};" \
373 "setenv bootargs root=/dev/ram0 rw " \
374 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
382 "setenv bootargs root=/dev/nfs rw " \
383 "nfsroot=${serverip}:${rootpath} " \
384 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
389 /* Define a command string that is automatically executed when no character
390 * is read on the console interface withing "Boot Delay" after reset.
392 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
393 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
395 #ifdef CONFIG_BOOT_ROOT_INITRD
396 #define CONFIG_BOOTCOMMAND \
400 "setenv bootargs root=/dev/ram0 rw " \
401 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
403 #endif /* CONFIG_BOOT_ROOT_INITRD */
405 #ifdef CONFIG_BOOT_ROOT_NFS
406 #define CONFIG_BOOTCOMMAND \
410 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
411 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
413 #endif /* CONFIG_BOOT_ROOT_NFS */
415 /* Add support for a few extra bootp options like:
417 * - DNS (up to 2 servers)
418 * - Send hostname to DHCP server
420 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
421 CONFIG_BOOTP_BOOTFILESIZE | \
423 CONFIG_BOOTP_DNS2 | \
424 CONFIG_BOOTP_SEND_HOSTNAME)
426 /* undef this to save memory */
429 /* Monitor Command Prompt */
430 #define CFG_PROMPT "=> "
432 #undef CFG_HUSH_PARSER
433 #ifdef CFG_HUSH_PARSER
434 #define CFG_PROMPT_HUSH_PS2 "> "
437 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
438 * of an image is printed by image commands like bootm or iminfo.
440 #define CONFIG_TIMESTAMP
442 /* If this variable is defined, an environment variable named "ver"
443 * is created by U-Boot showing the U-Boot version.
445 #define CONFIG_VERSION_VARIABLE
449 * Command line configuration.
451 #include <config_cmd_default.h>
453 #define CONFIG_CMD_ASKENV
454 #define CONFIG_CMD_ELF
455 #define CONFIG_CMD_I2C
456 #define CONFIG_CMD_IMMAP
457 #define CONFIG_CMD_PING
458 #define CONFIG_CMD_REGINFO
459 #define CONFIG_CMD_SDRAM
461 #undef CONFIG_CMD_KGDB
463 #if defined(CONFIG_ETHER_ON_FCC)
464 #define CONFIG_CMD_CMD_MII
468 #undef CONFIG_WATCHDOG /* disable the watchdog */
470 /* Where do the internal registers live? */
471 #define CFG_IMMR 0xF0000000
473 /*****************************************************************************
475 * You should not have to modify any of the following settings
477 *****************************************************************************/
479 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
480 #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
481 #define CONFIG_CPM2 1 /* Has a CPM2 */
485 * Miscellaneous configurable options
487 #if defined(CONFIG_CMD_KGDB)
488 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
490 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
493 /* Print Buffer Size */
494 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
496 #define CFG_MAXARGS 32 /* max number of command args */
498 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
500 #define CFG_LOAD_ADDR 0x400000 /* default load address */
501 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
503 #define CFG_ALT_MEMTEST /* Select full-featured memory test */
504 #define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
505 /* the exception vector table */
506 /* to the end of the DRAM */
507 /* less monitor and malloc area */
508 #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
509 #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
511 + CFG_ENV_SECT_SIZE \
514 #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
515 - CFG_MEM_END_USAGE )
517 /* valid baudrates */
518 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
521 * Low Level Configuration Settings
522 * (address mappings, register initial values, etc.)
523 * You should know what you are doing if you make changes here.
526 #define CFG_FLASH_BASE CFG_FLASH0_BASE
527 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
528 #define CFG_SDRAM_BASE CFG_SDRAM0_BASE
529 #define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
531 /*-----------------------------------------------------------------------
532 * Hard Reset Configuration Words
534 #if defined(CFG_SBC_BOOT_LOW)
535 # define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
537 # define CFG_SBC_HRCW_BOOT_FLAGS (0)
538 #endif /* defined(CFG_SBC_BOOT_LOW) */
540 /* get the HRCW ISB field from CFG_IMMR */
541 #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
542 ((CFG_IMMR & 0x01000000) >> 7) | \
543 ((CFG_IMMR & 0x00100000) >> 4) )
545 #define CFG_HRCW_MASTER ( HRCW_BPS11 | \
547 CFG_SBC_HRCW_IMMR | \
552 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
553 CFG_SBC_HRCW_BOOT_FLAGS )
556 #define CFG_HRCW_SLAVE1 0
557 #define CFG_HRCW_SLAVE2 0
558 #define CFG_HRCW_SLAVE3 0
559 #define CFG_HRCW_SLAVE4 0
560 #define CFG_HRCW_SLAVE5 0
561 #define CFG_HRCW_SLAVE6 0
562 #define CFG_HRCW_SLAVE7 0
564 /*-----------------------------------------------------------------------
565 * Definitions for initial stack pointer and data area (in DPRAM)
567 #define CFG_INIT_RAM_ADDR CFG_IMMR
568 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
569 #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
570 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
571 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
573 /*-----------------------------------------------------------------------
574 * Start addresses for the final memory configuration
575 * (Set up by the startup code)
576 * Please note that CFG_SDRAM_BASE _must_ start at 0
577 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
579 #define CFG_MONITOR_BASE CFG_FLASH0_BASE
581 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
585 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
586 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
589 * For booting Linux, the board info and command line data
590 * have to be in the first 8 MB of memory, since this is
591 * the maximum mapped by the Linux kernel during initialization.
593 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
595 /*-----------------------------------------------------------------------
596 * FLASH and environment organization
598 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
599 #define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
601 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
602 #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
605 # define CFG_ENV_IS_IN_FLASH 1
607 # ifdef CFG_ENV_IN_OWN_SECT
608 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
609 # define CFG_ENV_SECT_SIZE 0x40000
611 # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
612 # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
613 # define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
614 # endif /* CFG_ENV_IN_OWN_SECT */
617 # define CFG_ENV_IS_IN_NVRAM 1
618 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
619 # define CFG_ENV_SIZE 0x200
620 #endif /* CFG_RAMBOOT */
622 /*-----------------------------------------------------------------------
623 * Cache Configuration
625 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
627 #if defined(CONFIG_CMD_KGDB)
628 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
631 /*-----------------------------------------------------------------------
632 * HIDx - Hardware Implementation-dependent Registers 2-11
633 *-----------------------------------------------------------------------
634 * HID0 also contains cache control - initially enable both caches and
635 * invalidate contents, then the final state leaves only the instruction
636 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
637 * but Soft reset does not.
639 * HID1 has only read-only information - nothing to set.
641 #define CFG_HID0_INIT (HID0_ICE |\
648 #define CFG_HID0_FINAL (HID0_ICE |\
654 /*-----------------------------------------------------------------------
655 * RMR - Reset Mode Register
656 *-----------------------------------------------------------------------
660 /*-----------------------------------------------------------------------
661 * BCR - Bus Configuration 4-25
662 *-----------------------------------------------------------------------
664 #define CFG_BCR (BCR_ETM)
666 /*-----------------------------------------------------------------------
667 * SIUMCR - SIU Module Configuration 4-31
668 *-----------------------------------------------------------------------
671 #define CFG_SIUMCR (SIUMCR_DPPC11 |\
677 /*-----------------------------------------------------------------------
678 * SYPCR - System Protection Control 11-9
679 * SYPCR can only be written once after reset!
680 *-----------------------------------------------------------------------
681 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
683 #if defined(CONFIG_WATCHDOG)
684 #define CFG_SYPCR (SYPCR_SWTC |\
692 #define CFG_SYPCR (SYPCR_SWTC |\
698 #endif /* CONFIG_WATCHDOG */
700 /*-----------------------------------------------------------------------
701 * TMCNTSC - Time Counter Status and Control 4-40
702 *-----------------------------------------------------------------------
703 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
704 * and enable Time Counter
706 #define CFG_TMCNTSC (TMCNTSC_SEC |\
711 /*-----------------------------------------------------------------------
712 * PISCR - Periodic Interrupt Status and Control 4-42
713 *-----------------------------------------------------------------------
714 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
717 #define CFG_PISCR (PISCR_PS |\
721 /*-----------------------------------------------------------------------
722 * SCCR - System Clock Control 9-8
723 *-----------------------------------------------------------------------
727 /*-----------------------------------------------------------------------
728 * RCCR - RISC Controller Configuration 13-7
729 *-----------------------------------------------------------------------
734 * Initialize Memory Controller:
736 * Bank Bus Machine PortSz Device
737 * ---- --- ------- ------ ------
738 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
739 * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
740 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
741 * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
742 * 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
743 * 5 60x GPCM 8 bit EEPROM (8KB)
744 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
745 * 7 60x GPCM 8 bit LEDs, switches
747 * (*) This configuration requires the SBC8260 be configured
748 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
749 * the on board FLASH. In other words, JP24 should have
750 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
754 /*-----------------------------------------------------------------------
755 * BR0,BR1 - Base Register
756 * Ref: Section 10.3.1 on page 10-14
757 * OR0,OR1 - Option Register
758 * Ref: Section 10.3.2 on page 10-18
759 *-----------------------------------------------------------------------
762 /* Bank 0,1 - FLASH SIMM
764 * This expects the FLASH SIMM to be connected to *CS0
765 * It consists of 4 AM29F080B parts.
767 * Note: For the 4 MB SIMM, *CS1 is unused.
770 /* BR0 is configured as follows:
772 * - Base address of 0x40000000
774 * - Data errors checking is disabled
775 * - Read and write access
777 * - Access are handled by the memory controller according to MSEL
778 * - Not used for atomic operations
779 * - No data pipelining is done
782 #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
787 /* OR0 is configured as follows:
790 * - *BCTL0 is asserted upon access to the current memory bank
791 * - *CW / *WE are negated a quarter of a clock earlier
792 * - *CS is output at the same time as the address lines
793 * - Uses a clock cycle length of 5
794 * - *PSDVAL is generated internally by the memory controller
795 * unless *GTA is asserted earlier externally.
796 * - Relaxed timing is generated by the GPCM for accesses
797 * initiated to this memory region.
798 * - One idle clock is inserted between a read access from the
799 * current bank and the next access.
801 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
808 /*-----------------------------------------------------------------------
809 * BR2,BR3 - Base Register
810 * Ref: Section 10.3.1 on page 10-14
811 * OR2,OR3 - Option Register
812 * Ref: Section 10.3.2 on page 10-16
813 *-----------------------------------------------------------------------
816 /* Bank 2,3 - SDRAM DIMM
819 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
821 * Note: *CS3 is unused for this DIMM
824 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
826 * - Base address of 0x00000000
827 * - 64 bit port size (60x bus only)
828 * - Data errors checking is disabled
829 * - Read and write access
831 * - Access are handled by the memory controller according to MSEL
832 * - Not used for atomic operations
833 * - No data pipelining is done
836 #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
841 #define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
846 /* With a 16 MB DIMM, the OR2 is configured as follows:
849 * - 2 internal banks per device
850 * - Row start address bit is A9 with PSDMR[PBI] = 0
851 * - 11 row address lines
852 * - Back-to-back page mode
853 * - Internal bank interleaving within save device enabled
855 #if (CFG_SDRAM0_SIZE == 16)
856 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
858 ORxS_ROWST_PBI0_A9 |\
862 /* With a 64 MB DIMM, the OR2 is configured as follows:
865 * - 4 internal banks per device
866 * - Row start address bit is A8 with PSDMR[PBI] = 0
867 * - 12 row address lines
868 * - Back-to-back page mode
869 * - Internal bank interleaving within save device enabled
871 #if (CFG_SDRAM0_SIZE == 64)
872 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
874 ORxS_ROWST_PBI0_A8 |\
878 /*-----------------------------------------------------------------------
879 * PSDMR - 60x Bus SDRAM Mode Register
880 * Ref: Section 10.3.3 on page 10-21
881 *-----------------------------------------------------------------------
884 /* Address that the DIMM SPD memory lives at.
886 #define SDRAM_SPD_ADDR 0x54
888 #if (CFG_SDRAM0_SIZE == 16)
889 /* With a 16 MB DIMM, the PSDMR is configured as follows:
891 * - Bank Based Interleaving,
893 * - Address Multiplexing where A5 is output on A14 pin
894 * (A6 on A15, and so on),
895 * - use address pins A16-A18 as bank select,
896 * - A9 is output on SDA10 during an ACTIVATE command,
897 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
898 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
900 * - earliest timing for READ/WRITE command after ACTIVATE command is
902 * - earliest timing for PRECHARGE after last data was read is 1 clock,
903 * - earliest timing for PRECHARGE after last data was written is 1 clock,
904 * - CAS Latency is 2.
906 #define CFG_PSDMR (PSDMR_RFEN |\
907 PSDMR_SDAM_A14_IS_A5 |\
908 PSDMR_BSMA_A16_A18 |\
909 PSDMR_SDA10_PBI0_A9 |\
918 #if (CFG_SDRAM0_SIZE == 64)
919 /* With a 64 MB DIMM, the PSDMR is configured as follows:
921 * - Bank Based Interleaving,
923 * - Address Multiplexing where A5 is output on A14 pin
924 * (A6 on A15, and so on),
925 * - use address pins A14-A16 as bank select,
926 * - A9 is output on SDA10 during an ACTIVATE command,
927 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
928 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
930 * - earliest timing for READ/WRITE command after ACTIVATE command is
932 * - earliest timing for PRECHARGE after last data was read is 1 clock,
933 * - earliest timing for PRECHARGE after last data was written is 1 clock,
934 * - CAS Latency is 2.
936 #define CFG_PSDMR (PSDMR_RFEN |\
937 PSDMR_SDAM_A14_IS_A5 |\
938 PSDMR_BSMA_A14_A16 |\
939 PSDMR_SDA10_PBI0_A9 |\
949 * Shoot for approximately 1MHz on the prescaler.
951 #if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
952 #define CFG_MPTPR MPTPR_PTP_DIV64
953 #elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
954 #define CFG_MPTPR MPTPR_PTP_DIV32
956 #warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
957 #define CFG_MPTPR MPTPR_PTP_DIV32
962 /* Bank 4 - On board SDRAM
964 * This is not implemented yet.
967 /*-----------------------------------------------------------------------
968 * BR6 - Base Register
969 * Ref: Section 10.3.1 on page 10-14
970 * OR6 - Option Register
971 * Ref: Section 10.3.2 on page 10-18
972 *-----------------------------------------------------------------------
975 /* Bank 6 - On board FLASH
977 * This expects the on board FLASH SIMM to be connected to *CS6
978 * It consists of 1 AM29F016A part.
980 #if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
982 /* BR6 is configured as follows:
984 * - Base address of 0x60000000
986 * - Data errors checking is disabled
987 * - Read and write access
989 * - Access are handled by the memory controller according to MSEL
990 * - Not used for atomic operations
991 * - No data pipelining is done
994 # define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
999 /* OR6 is configured as follows:
1002 * - *BCTL0 is asserted upon access to the current memory bank
1003 * - *CW / *WE are negated a quarter of a clock earlier
1004 * - *CS is output at the same time as the address lines
1005 * - Uses a clock cycle length of 5
1006 * - *PSDVAL is generated internally by the memory controller
1007 * unless *GTA is asserted earlier externally.
1008 * - Relaxed timing is generated by the GPCM for accesses
1009 * initiated to this memory region.
1010 * - One idle clock is inserted between a read access from the
1011 * current bank and the next access.
1013 # define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1019 #endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1021 /*-----------------------------------------------------------------------
1022 * BR7 - Base Register
1023 * Ref: Section 10.3.1 on page 10-14
1024 * OR7 - Option Register
1025 * Ref: Section 10.3.2 on page 10-18
1026 *-----------------------------------------------------------------------
1029 /* Bank 7 - LEDs and switches
1031 * LEDs are at 0x00001 (write only)
1032 * switches are at 0x00001 (read only)
1036 /* BR7 is configured as follows:
1038 * - Base address of 0xA0000000
1040 * - Data errors checking is disabled
1041 * - Read and write access
1043 * - Access are handled by the memory controller according to MSEL
1044 * - Not used for atomic operations
1045 * - No data pipelining is done
1048 # define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
1053 /* OR7 is configured as follows:
1056 * - *BCTL0 is asserted upon access to the current memory bank
1057 * - *CW / *WE are negated a quarter of a clock earlier
1058 * - *CS is output at the same time as the address lines
1059 * - Uses a clock cycle length of 15
1060 * - *PSDVAL is generated internally by the memory controller
1061 * unless *GTA is asserted earlier externally.
1062 * - Relaxed timing is generated by the GPCM for accesses
1063 * initiated to this memory region.
1064 * - One idle clock is inserted between a read access from the
1065 * current bank and the next access.
1067 # define CFG_OR7_PRELIM (ORxG_AM_MSK |\
1073 #endif /* CFG_LED_BASE */
1076 * Internal Definitions
1080 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1081 #define BOOTFLAG_WARM 0x02 /* Software reboot */
1083 #endif /* __CONFIG_H */