3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
7 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
9 * SPDX-License-Identifier: GPL-2.0+
15 #undef USE_VGA_GRAPHICS
18 * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
19 * 0x74000000 .... 0x740FFFFF -> CS#6
20 * 0x74100000 .... 0x741FFFFF -> CS#7
21 * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
22 * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
23 * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
24 * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
25 * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
26 * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
27 * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
28 * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
30 * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
31 * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
32 * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
33 * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
34 * 0xEED00000 .... 0xEED00003 -> PCI-Bus
35 * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
36 * 0xEF40003F .... 0xEF5FFFFF -> reserved
37 * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
38 * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
39 * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
40 * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
41 * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
42 * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
47 #define CONFIG_405GP 1
49 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
51 #define CONFIG_BOARD_EARLY_INIT_F 1
52 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
55 * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
56 * If undefined, IDE access uses a seperat emulation with higher access speed.
57 * Consider to inform your Linux IDE driver about the different addresses!
58 * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
60 #define IDE_USES_ISA_EMULATION
62 /*-----------------------------------------------------------------------
64 *----------------------------------------------------------------------*/
65 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
66 #define CONFIG_SYS_NS16550
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE 1
69 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
72 * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
74 #define CONFIG_SYS_CLK_FREQ 33333333
77 * define CONFIG_BAUDRATE to the baudrate value you want to use as default
79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
82 #define CONFIG_PREBOOT "echo;" \
83 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
86 #undef CONFIG_BOOTARGS
88 #define CONFIG_EXTRA_ENV_SETTINGS \
90 "nfsargs=setenv bootargs root=/dev/nfs rw " \
91 "nfsroot=${serverip}:${rootpath}\0" \
92 "ramargs=setenv bootargs root=/dev/ram rw\0" \
93 "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \
94 "rootfstype=jffs2\0" \
95 "addip=setenv bootargs ${bootargs} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
97 ":${hostname}:${netdev}:off panic=1\0" \
98 "addcons=setenv bootargs ${bootargs} " \
99 "console=ttyS0,${baudrate}\0" \
100 "flash_nfs=run nfsargs addip addcons;" \
101 "bootm ${kernel_addr}\0" \
102 "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \
103 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
105 "rootpath=/opt/eldk/ppc_4xx\0" \
106 "bootfile=/tftpboot/sc3/uImage\0" \
107 "u-boot=/tftpboot/sc3/u-boot.bin\0" \
108 "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \
109 "kernel_addr=FFE08000\0" \
111 #undef CONFIG_BOOTCOMMAND
113 #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
114 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
116 #if 1 /* feel free to disable for development */
117 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
118 #define CONFIG_AUTOBOOT_PROMPT \
119 "\nSC3 - booting... stop with ENTER\n"
120 #define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
121 #define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
125 * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
126 * the CONFIG_BOOTDELAY delay to boot your machine
128 #define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
131 * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
132 * set different values at the u-boot prompt
134 #ifdef USE_VGA_GRAPHICS
135 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
137 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
140 * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
141 * This reserves memory bank #4 for this purpose
143 #undef CONFIG_ISP1161_PRESENT
145 #undef CONFIG_LOADS_ECHO /* no echo on for serial download */
146 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
148 /* #define CONFIG_EEPRO100_SROM_WRITE */
149 /* #define CONFIG_SHOW_MAC */
150 #define CONFIG_EEPRO100
152 #define CONFIG_PPC4xx_EMAC
153 #define CONFIG_MII 1 /* add 405GP MII PHY management */
154 #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
159 #define CONFIG_BOOTP_BOOTFILESIZE
160 #define CONFIG_BOOTP_BOOTPATH
161 #define CONFIG_BOOTP_GATEWAY
162 #define CONFIG_BOOTP_HOSTNAME
166 * Command line configuration.
168 #include <config_cmd_default.h>
171 #define CONFIG_CMD_CACHE
172 #define CONFIG_CMD_DATE
173 #define CONFIG_CMD_DHCP
174 #define CONFIG_CMD_ELF
175 #define CONFIG_CMD_I2C
176 #define CONFIG_CMD_IDE
177 #define CONFIG_CMD_IRQ
178 #define CONFIG_CMD_JFFS2
179 #define CONFIG_CMD_MII
180 #define CONFIG_CMD_NAND
181 #define CONFIG_CMD_NET
182 #define CONFIG_CMD_PCI
183 #define CONFIG_CMD_PING
184 #define CONFIG_CMD_SOURCE
187 #undef CONFIG_WATCHDOG /* watchdog disabled */
190 * Miscellaneous configurable options
192 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
193 #define CONFIG_SYS_PROMPT "SC3> " /* Monitor Command Prompt */
194 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
196 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
198 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
199 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
201 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
202 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
205 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
206 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
207 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
208 * The Linux BASE_BAUD define should match this configuration.
209 * baseBaud = cpuClock/(uartDivisor*16)
210 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
211 * set Linux BASE_BAUD to 403200.
213 * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
214 * (see 405GP datasheet for descritpion)
216 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
217 #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
218 #define CONFIG_SYS_BASE_BAUD 921600 /* internal clock */
220 /* The following table includes the supported baudrates */
221 #define CONFIG_SYS_BAUDRATE_TABLE \
222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
224 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
225 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
227 /*-----------------------------------------------------------------------
229 *-----------------------------------------------------------------------
231 #define CONFIG_SYS_I2C
232 #define CONFIG_SYS_I2C_PPC4XX
233 #define CONFIG_SYS_I2C_PPC4XX_CH0
237 #define I2C_TRISTATE 0
239 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
240 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* mask valid bits */
242 #define CONFIG_RTC_DS1337
243 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
245 /*-----------------------------------------------------------------------
247 *-----------------------------------------------------------------------
249 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
250 #define PCI_HOST_FORCE 1 /* configure as pci host */
251 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
253 #define CONFIG_PCI /* include pci support */
254 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
255 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
256 #define CONFIG_PCI_PNP /* do pci plug-and-play */
257 /* resource configuration */
259 /* If you want to see, whats connected to your PCI bus */
260 /* #define CONFIG_PCI_SCAN_SHOW */
262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
263 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
264 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
265 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
266 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
267 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
268 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
269 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
271 /*-----------------------------------------------------------------------
272 * External peripheral base address
273 *-----------------------------------------------------------------------
275 #if !defined(CONFIG_CMD_IDE)
277 #undef CONFIG_IDE_LED /* no led for ide supported */
278 #undef CONFIG_IDE_RESET /* no reset for ide supported */
280 /*-----------------------------------------------------------------------
282 *-----------------------------------------------------------------------
285 #define CONFIG_START_IDE 1 /* check, if use IDE */
287 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
288 #undef CONFIG_IDE_LED /* no led for ide supported */
289 #undef CONFIG_IDE_RESET /* no reset for ide supported */
292 #define CONFIG_DOS_PARTITION
293 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
295 #ifndef IDE_USES_ISA_EMULATION
297 /* New and faster access */
298 #define CONFIG_SYS_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
300 /* How many IDE busses are available */
301 #define CONFIG_SYS_IDE_MAXBUS 1
303 /* What IDE ports are available */
304 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x000 /* first is available */
305 #undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */
307 /* access to the data port is calculated:
308 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
309 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
311 /* access to the registers is calculated:
312 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
313 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
315 /* access to the alternate register is calculated:
316 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
317 #define CONFIG_SYS_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
319 #else /* IDE_USES_ISA_EMULATION */
321 #define CONFIG_SYS_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
323 /* How many IDE busses are available */
324 #define CONFIG_SYS_IDE_MAXBUS 1
326 /* What IDE ports are available */
327 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* first is available */
328 #undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */
330 /* access to the data port is calculated:
331 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
332 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
334 /* access to the registers is calculated:
335 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
336 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
338 /* access to the alternate register is calculated:
339 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
340 #define CONFIG_SYS_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
342 #endif /* IDE_USES_ISA_EMULATION */
347 #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
348 #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
349 #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
352 /*-----------------------------------------------------------------------
353 * Start addresses for the final memory configuration
354 * (Set up by the startup code)
355 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
357 * CONFIG_SYS_FLASH_BASE -> start address of internal flash
358 * CONFIG_SYS_MONITOR_BASE -> start of u-boot
360 #define CONFIG_SYS_SDRAM_BASE 0x00000000
361 #define CONFIG_SYS_FLASH_BASE 0xFFE00000
363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
364 #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
365 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
368 * For booting Linux, the board info and command line data
369 * have to be in the first 8 MiB of memory, since this is
370 * the maximum mapped by the Linux kernel during initialization.
372 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
373 /*-----------------------------------------------------------------------
374 * FLASH organization ## FIXME: lookup in datasheet
376 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
377 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
379 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
380 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
381 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
382 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
383 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
384 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
385 #define CONFIG_SYS_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */
387 #define CONFIG_ENV_IS_IN_FLASH 1
388 #ifdef CONFIG_ENV_IS_IN_FLASH
389 #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
390 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
391 #define CONFIG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
393 /* Address and size of Redundant Environment Sector */
394 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
395 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
398 /* let us changing anything in our environment */
399 #define CONFIG_ENV_OVERWRITE
404 #define CONFIG_SYS_MAX_NAND_DEVICE 1
405 #define CONFIG_SYS_NAND_BASE 0x77D00000
407 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
409 /* No command line, one static partition */
410 #undef CONFIG_CMD_MTDPARTS
411 #define CONFIG_JFFS2_DEV "nand0"
412 #define CONFIG_JFFS2_PART_SIZE 0x01000000
413 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
416 * Init Memory Controller:
420 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
421 #define FLASH_BASE1_PRELIM 0
423 /*-----------------------------------------------------------------------
424 * Some informations about the internal SRAM (OCM=On Chip Memory)
426 * CONFIG_SYS_OCM_DATA_ADDR -> location
427 * CONFIG_SYS_OCM_DATA_SIZE -> size
430 #define CONFIG_SYS_TEMP_STACK_OCM 1
431 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
432 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
434 /*-----------------------------------------------------------------------
435 * Definitions for initial stack pointer and data area (in DPRAM):
436 * - we are using the internal 4k SRAM, so we don't need data cache mapping
437 * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
438 * - Stackpointer will be located to
439 * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
440 * in arch/powerpc/cpu/ppc4xx/start.S
443 #undef CONFIG_SYS_INIT_DCACHE_CS
444 /* Where the internal SRAM starts */
445 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
446 /* Where the internal SRAM ends (only offset) */
447 #define CONFIG_SYS_INIT_RAM_SIZE 0x0F00
451 CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address
456 CONFIG_SYS_GBL_DATA_OFFSET ----> ------------
460 CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address
464 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
465 /* Initial value of the stack pointern in internal SRAM */
466 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
468 /* ################################################################################### */
469 /* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
470 /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
472 /* This chip select accesses the boot device */
473 /* It depends on boot select switch if this device is 16 or 8 bit */
475 #undef CONFIG_SYS_EBC_PB0AP
476 #undef CONFIG_SYS_EBC_PB0CR
478 #undef CONFIG_SYS_EBC_PB1AP
479 #undef CONFIG_SYS_EBC_PB1CR
481 #undef CONFIG_SYS_EBC_PB2AP
482 #undef CONFIG_SYS_EBC_PB2CR
484 #undef CONFIG_SYS_EBC_PB3AP
485 #undef CONFIG_SYS_EBC_PB3CR
487 #undef CONFIG_SYS_EBC_PB4AP
488 #undef CONFIG_SYS_EBC_PB4CR
490 #undef CONFIG_SYS_EBC_PB5AP
491 #undef CONFIG_SYS_EBC_PB5CR
493 #undef CONFIG_SYS_EBC_PB6AP
494 #undef CONFIG_SYS_EBC_PB6CR
496 #undef CONFIG_SYS_EBC_PB7AP
497 #undef CONFIG_SYS_EBC_PB7CR
499 #define CONFIG_SYS_EBC_CFG 0xb84ef000
501 #undef CONFIG_SDRAM_BANK0 /* use private SDRAM initialization */
502 #undef CONFIG_SPD_EEPROM
505 * Define this to get more information about system configuration
507 /* #define SC3_DEBUGOUT */
510 /***********************************************************************
511 * External peripheral base address
512 ***********************************************************************/
514 #define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000
516 Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
517 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
518 das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
519 auf ISA- und PCI-Zyklen)
521 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
522 /*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0x79000000 */
524 /************************************************************
526 ************************************************************/
528 #ifdef USE_VGA_GRAPHICS
529 #define CONFIG_VIDEO /* To enable video controller support */
530 #define CONFIG_VIDEO_CT69000
531 #define CONFIG_CFB_CONSOLE
532 /* #define CONFIG_VIDEO_LOGO */
533 #define CONFIG_VGA_AS_SINGLE_DEVICE
534 #define CONFIG_VIDEO_SW_CURSOR
535 /* #define CONFIG_VIDEO_HW_CURSOR */
536 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
538 #define VIDEO_HW_RECTFILL
539 #define VIDEO_HW_BITBLT
543 /************************************************************
545 ************************************************************/
546 #define CONFIG_SC3_VERSION "r1.4"
548 #define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
550 #endif /* __CONFIG_H */